OLTs with meshed interconnection

Patent metadata

Field	Value
Publication number	US-12504593-B2
Application number	US-202318201040-A
Country	US
Kind code	B2
Filing date	May 23, 2023
Priority date	Aug 9, 2022
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

A system with OLTs having a meshed interconnection.

First claim

The invention claimed is:

1 . A network architecture comprising:
(a) a first optical line terminal that includes a first single backplane circuit board that does not include any detachably engageable cards that include PON ports on said engageable cards; (b) said first single backplane circuit board including at least one first network side interface for receiving data from and providing data to a core network; (c) said first single backplane circuit board including a plurality of PON ports for receiving data from an optical PON network and providing data to said optical PON network, wherein said first single backplane circuit board includes no more than 16 said PON ports; (d) said first single backplane circuit board supporting a processor, at least one transmitter, and at least one optical sensor, configured to provide and receive data to said plurality of PON ports and configured to provide and receive data from said at least one network side interface; (e) said first single backplane, said processor, said at least one transmitter, and said at least one optical sensor all enclosed within a first OLT housing; (f) a server including a virtualized management service, where said virtualized management service selectively provisions said first optical line terminal for a first subscriber from a first one of said plurality of PON ports of said first optical line terminal to a second one of said plurality of PON ports of said first optical line terminal.

2 . The network architecture of claim 1 further comprising a second optical line terminal that includes a second single backplane circuit board that does not include any detachably engageable cards that include PON ports on said engageable cards, said second single backplane circuit board including at least one second network side interface for receiving data from and providing data to said core network, said second single backplane circuit board including a plurality of PON ports for receiving data from an optical PON network and providing data to said optical PON network, wherein said second single backplane circuit board includes no more than 16 said PON ports, said second single backplane circuit board supporting a processor, at least one transmitter, and at least one optical sensor, configured to provide and receive data to said plurality of PON ports and configured to provide and receive data from said at least one network side interface, and said second single backplane, said processor, said at least one transmitter, and said at least one optical sensor all enclosed within a second OLT housing.

3 . The network architecture of claim 2 further comprising
(a) a switch enclosed within a switch housing, where said switch housing, said first OLT housing, and said second OLT housing are separate from one another;
(b) said at least one first network side interface interconnected to at least one port of said switch with at least one cable;
(c) said at least one second network side interface interconnected to at least one port of said switch with at least one cable;
(d) said switch interconnected to said core network.

4 . The network architecture of claim 1 further comprising a second optical line terminal that includes a second single backplane circuit board that does not include any detachably engageable cards that include PON ports on said engageable cards, said second single backplane circuit board including at least one second network side interface for receiving data from and providing data to said core network, said second single backplane circuit board including a plurality of PON ports for receiving data from an optical PON network and providing data to said optical PON network, wherein said second single backplane circuit board includes no more than 16 said PON ports, said second single backplane circuit board supporting a processor, at least one transmitter, and at least one optical sensor, configured to provide and receive data to said plurality of PON ports and configured to provide and receive data from said at least one network side interface, and said second single backplane, said processor, said at least one transmitter, and said at least one optical sensor all enclosed within a second OLT housing, where said first optical line terminal and said second optical line terminal support the same set of optical network terminals.

5 . A network architecture comprising:
(a) a first terminal that includes a first single backplane circuit board that does not include any detachably engageable cards that include network ports on said engageable cards; (b) said first single backplane circuit board including at least one first network side interface for receiving data from and providing data to a core network; (c) said first single backplane circuit board including a plurality of first network ports for receiving data from a data network and providing data to said data network, wherein said first single backplane circuit board includes no more than 16 said first network ports; (d) said first single backplane circuit board supporting a first processor, at least one first transmitter, and at least one first optical sensor, configured to provide and receive data to said plurality of first network ports and configured to provide and receive data from said at least one first network side interface; (e) said first single backplane, said first processor, said at least one first transmitter, and said at least one first optical sensor all enclosed within a first housing; (f) a second terminal that includes a second single backplane circuit board that does not include any detachably engageable cards that include network ports on said engageable cards; (g) said second single backplane circuit board including at least one second network side interface for receiving data from and providing data to said core network; (h) said second single backplane circuit board including a plurality of second network ports for receiving data from said data network and providing data to said data network, wherein said second single backplane circuit board includes no more than 16 said second network ports; (i) said second single backplane circuit board supporting a second processor, at least one second transmitter, and at least one second optical sensor, configured to provide and receive data to said plurality of second network ports and configured to provide and receive data from said at least one second network side interface; (i) said second single backplane, said second processor, said at least one second transmitter, and said at least one second optical sensor all enclosed within a second housing; (k) said first processor processing first management functions for said first terminal and said second processor processing second management functions for said second terminal; (l) said first processor of said first terminal redistributing a portion of its processing of said first management functions to said second processor of said second terminal to process said portion of said first management functions on behalf of said first processor for said first terminal.

Assignees

• Arris Entpr Llc

Inventors

• Pratt Bruce C
• Warner Shawn W
• Bowler David
• Colarusso Theodore A

Classifications

• H04J14/0282

  WDM tree architectures · CPC title

• H05K1/0274

  Optical details, e.g. printed circuits comprising integral optical means (H05K1/0269 takes precedence; coupling light guides with opto-electronic components G02B6/42) · CPC title

• G02B6/3897

  Connectors fixed to housings, casing, frames or circuit boards (G02B6/44528 takes precedence) · CPC title

• H04L12/2861

  Point-to-multipoint connection from the data network to the subscribers · CPC title

• H04B10/27

  Arrangements for networking · CPC title