Display panel and method for manufacturing the same, and display device

Patent metadata

Field	Value
Publication number	US-12501792-B2
Application number	US-202117923934-A
Country	US
Kind code	B2
Filing date	Nov 4, 2021
Priority date	Feb 9, 2021
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

A display panel includes: a substrate; at least one first signal line disposed on the substrate and located in a peripheral region; at least one second signal line disposed on the substrate and located in the peripheral region; an insulating layer covering the at least one first signal line and the at least one second signal line; and a shielding signal line covering the at least one groove. The at least one second signal line and the at least one first signal line are arranged in a same layer. A surface of the insulating layer away from the substrate has at least one groove. An orthogonal projection, on the substrate, of a bottom surface of a groove is located between orthogonal projections, on the substrate, of a first signal line and a second signal line.

First claim

What is claimed is:

1 . A display panel having a display region and a peripheral region located on at least one side of the display region, the display panel comprising:
a substrate; at least one first signal line disposed on the substrate and located in the peripheral region; at least one second signal line disposed on the substrate and located in the peripheral region, wherein the at least one second signal line and the at least one first signal line are arranged in a same layer; an insulating layer covering the at least one first signal line and the at least one second signal line, wherein a surface of the insulating layer away from the substrate has at least one groove, and an orthogonal projection, on the substrate, of a bottom surface of a groove of the at least one groove is located between adjacent two edges of orthogonal projections, on the substrate, of a first signal line of the at least one first signal line and a second signal line of the at least one second signal line; a shielding signal line covering the at least one groove; a plurality of pixel circuits disposed on the substrate and located in the display region; and a driving circuit disposed on the substrate and located in the peripheral region; wherein the driving circuit is directly electrically connected to the plurality of pixel circuits, the first signal line and the second signal line; and the driving circuit is configured to provide driving signals to the plurality of pixel circuits in response to a first signal received at the first signal line and a second signal received at the second signal line, so as to drive the plurality of pixel circuits to operate.

2 . The display panel according to claim 1 , wherein in a direction perpendicular to a plane where the substrate is located, the bottom surface of the groove is closer to the substrate than at least one of a top surface of the first signal line and a top surface of the second signal line.

3 . The display panel according to claim 1 , wherein the first signal line is adjacent to the second signal line; and
a width of the bottom surface of the groove is less than or equal to a distance between the adjacent two edges of the orthogonal projections, on the substrate, of the first signal line and the second signal line.

4 . The display panel according to claim 1 , wherein a width of the bottom surface of the groove is in a range of 2 μm to 10 μm, inclusive.

5 . The display panel according to claim 1 , wherein the first signal line and the second signal line extends in a same direction; and
the groove extends in an extending direction of the first signal line and the second signal line.

6 . The display panel according to claim 1 , wherein the orthogonal projections, on the substrate, of the first signal line and the second signal line are located within an orthogonal projection, on the substrate, of the shielding signal line.

7 . The display panel according to claim 1 , wherein the shielding signal line is located in the peripheral region, and surrounds the display region.

8 . The display panel according to claim 1 , wherein the first signal line is configured to transmit the first signal; the second signal line is configured to transmit the second signal; the first signal and the second signal are pulse signals, and the first signal and the second signal are different; and
the shielding signal line is configured to transmit a direct current signal.

9 . The display panel according to claim 8 , wherein the first signal and the second signal have a same pulse cycle; and the first signal and the second signal have a phase difference.

10 . The display panel according to claim 9 , wherein the pulse cycle is in a range of 4 μs to 100 μs, inclusive.

11 . The display panel according to claim 1 , further comprising:
a plurality of light-emitting devices disposed on the substrate and located in the display region, wherein each light-emitting device of the plurality of light-emitting devices includes a first electrode and a second electrode, the first electrode is closer to the substrate than the second electrode, and the second electrode is coupled to the shielding signal line.

12 . The display panel according to claim 11 , wherein the first electrode of the light-emitting device and the shielding signal line are arranged in a same layer; and
the insulating layer has a double-layer structure.

13 . The display panel according to claim 11 , wherein the first electrode of the light-emitting device is farther away from the substrate than the shielding signal line; and
the insulating layer has a single-layer structure.

14 . A display device, comprising:
the display panel according to claim 1 ; and a control chip coupled to the display panel, the control chip being configured to provide signals for the display panel.

15 . A method for manufacturing a display panel, comprising:
providing a substrate, wherein the substrate has a display region and a peripheral region located on at least one side of the display region; forming at least one first signal line and at least one second signal line on the substrate and in the peripheral region; forming an insulating layer, wherein the insulating layer covers the at least one first signal line and the at least one second signal line, a surface of the insulating layer away from the substrate has at least one groove, and an orthogonal projection, on the substrate, of a bottom surface of a groove of the at least one groove is located between adjacent two edges of orthogonal projections, on the substrate, of a first signal line of the at least one first signal line and a second signal line of the at least one second signal line; and forming a shielding signal line, wherein the shielding signal line covers the at least one groove; the method further comprising: forming a plurality of pixel circuits on the substrate in the display region; and forming a driving circuit on the substrate and in the peripheral region, wherein the driving circuit is directly electrically connected to the plurality of pixel circuits, the first signal line and the second signal line; and the driving circuit is configured to provide driving signals to the plurality of pixel circuits in response to a first signal received at the first signal line and a second signal received at the second signal line, so as to drive the plurality of pixel circuits to operate.

16 . The method according to claim 15 , wherein forming the insulating layer includes:
forming an insulating material layer on the substrate on which the at least one first signal line and the at least one second signal line have been formed; forming a photoresist layer on the insulating material layer; exposing the photoresist layer through a halftone mask; developing the exposed photoresist layer, so as to obtain a photoresist completely-removed portion, at least one photoresist partially-retained portion and a photoresist completely-retained portion; etching the insulating material layer, so as to remove a portion of the insulating material layer corresponding to the photoresist completely-removed portion; removing the at least one photoresist partially-retained portion through an ashing process; etching a respective portion of the insulating material layer corresponding to each of the at least one photoresist partially-retained portion, so as to obtain the at least one groove; and stripping the photoresist completely-retained portion, so as to obtain the insulating layer.

17 . The display panel according to claim 2 , wherein the

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Lu Jiangnan
• Liu Libin
• Shang Guangliang
• Han Long
• Feng Yu
• Wang Li
• Li Mei

Classifications

• H10W42/20

  protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons · CPC title

• H10K59/124

  Insulating layers formed between TFT elements and OLED elements · CPC title

• H10K59/1201

  Manufacture or treatment · CPC title

• H10K59/126

  Shielding, e.g. light-blocking means over the TFTs · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title