Display apparatus

Patent metadata

Field	Value
Publication number	US-12501776-B2
Application number	US-202218701696-A
Country	US
Kind code	B2
Filing date	Oct 17, 2022
Priority date	Oct 27, 2021
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

A novel display apparatus is provided. The display apparatus includes a first layer and a second layer over the first layer. The first layer includes a functional circuit. The second layer includes a display unit including a plurality of pixels and a memory unit including a plurality of memory cells. Each of the plurality of pixels includes a pixel circuit and a light-emitting element over the pixel circuit. The functional circuit includes a display unit driver circuit and a control circuit. The memory unit has a function of storing image data that is to be output through the display unit driver circuit to the display unit. The memory cell includes a first transistor for retaining a potential corresponding to the image data, and a second transistor for reading the potential. The first transistor is provided in the second layer, and the second transistor is provided in the first layer.

First claim

The invention claimed is:

1 . A display apparatus comprising:
a first layer; a second layer over the first layer; and a third layer over the second layer, wherein the first layer comprises a functional circuit, wherein the second layer comprises a display unit comprising a plurality of pixels, wherein the third layer comprises a memory unit comprising a plurality of memory cells, wherein each of the plurality of pixels comprises a pixel circuit and a light-emitting element over the pixel circuit, wherein the functional circuit comprises a display unit driver circuit, and wherein the memory unit is configured to store image data that is to be output through the display unit driver circuit to the display unit.

2 . The display apparatus according to claim 1 ,
wherein one of the plurality of memory cells comprises:
a first transistor configured to retain a potential corresponding to the image data; and
a second transistor configured to read the potential,
wherein the first transistor is provided in the third layer, and wherein the second transistor is provided in the first layer.

3 . The display apparatus according to claim 2 ,
wherein a semiconductor layer comprising a channel formation region of the first transistor comprises a metal oxide, and wherein a semiconductor layer comprising a channel formation region of the second transistor comprises silicon.

4 . The display apparatus according to claim 1 ,
wherein the display unit driver circuit is provided in a region overlapping with the display unit.

5 . The display apparatus according to claim 1 ,
wherein the functional circuit comprises a control circuit, a sensor circuit, a communication circuit, and an input/output circuit.

6 . A display apparatus comprising:
a first layer; and a second layer over the first layer, wherein the first layer comprises:
a display unit driver circuit;
a memory unit driver circuit;
a control circuit; and
at least one of a sensor circuit, a communication circuit, and an input/output circuit,
wherein the second layer comprises:
a display unit comprising a plurality of pixels; and
a memory unit comprising a plurality of memory cells,
wherein each of the plurality of pixels comprises a pixel circuit and a light-emitting element over the pixel circuit, wherein the memory unit is configured to store image data that is to be output through the display unit driver circuit to the display unit, and wherein the display unit driver circuit, the memory unit driver circuit, the control circuit, and the one of the sensor circuit, the communication circuit, and the input/output circuit overlaps with the display unit.

7 . The display apparatus according to claim 6 ,
wherein one of the plurality of memory cells comprises:
a first transistor configured to retain a potential corresponding to the image data; and
a second transistor configured to read the potential,
wherein the first transistor is provided in the second layer, and wherein the second transistor is provided in the first layer.

8 . The display apparatus according to claim 7 ,
wherein a semiconductor layer comprising a channel formation region of the first transistor comprises a metal oxide, and wherein a semiconductor layer comprising a channel formation region of the second transistor comprises silicon.

9 . The display apparatus according to claim 6 ,
wherein, in a top view of the display apparatus, a first memory cell of the plurality of memory cells and a second memory cell of the plurality of memory cells sandwich the display unit.

10 . The display apparatus according to claim 6 ,
wherein the display unit comprises a plurality of sub-display units, and wherein the number of times of image rewriting of image data per unit time in a first sub-display unit of the plurality of sub-display units is smaller than the number of times of image rewriting of image data per unit time in a second sub-display unit of the plurality of sub-display units.

11 . The display apparatus according to claim 6 ,
wherein one of the plurality of memory cells comprises:
a first transistor; and
a second transistor,
wherein the first transistor is provided in the second layer, and wherein the second transistor is provided in the first layer.

12 . The display apparatus according to claim 11 ,
wherein a semiconductor layer comprising a channel formation region of the first transistor comprises a metal oxide, and wherein a semiconductor layer comprising a channel formation region of the second transistor comprises silicon.

13 . The display apparatus according to claim 8 ,
wherein the metal oxide comprises indium.

14 . The display apparatus according to claim 12 ,
wherein the metal oxide comprises indium.

Assignees

• Semiconductor Energy Lab

Inventors

• Matsuzaki Takanori
• Onuki tatsuya
• Kato Kiyoshi
• Okamoto Yuki
• Yamazaki Shunpei

Classifications

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0465

  Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness · CPC title

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title

• G09G2360/12

  Frame memory handling · CPC title