Display apparatus

Patent metadata

Field	Value
Publication number	US-12501774-B2
Application number	US-202318137713-A
Country	US
Kind code	B2
Filing date	Apr 21, 2023
Priority date	Sep 13, 2022
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

A display apparatus includes a substrate including a display area on which a display element is disposed, an emission control transistor which is disposed in the display area, includes a first semiconductor layer, and is connected to a pixel electrode of an organic light-emitting diode, a switching transistor disposed in the display area and including a second semiconductor layer, and a first initialization transistor disposed in the display area and including a third semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer each include a silicon semiconductor, the third semiconductor layer includes an oxide semiconductor, and at least one of the emission control transistor, the switching transistor, and the first initialization transistor includes a dual gate electrode.

First claim

What is claimed is:

1 . A display apparatus comprising:
a substrate comprising a display area on which a display element is disposed; an emission control transistor which is disposed in the display area, comprises a first semiconductor layer, and is connected to a pixel electrode of an organic light-emitting diode; a switching transistor disposed in the display area and comprising a second semiconductor layer; and a first initialization transistor disposed in the display area and comprising a third semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer each comprise a silicon semiconductor, the third semiconductor layer comprises an oxide semiconductor, and each of the emission control transistor, the switching transistor, and the first initialization transistor comprises a dual gate electrode.

2 . The display apparatus of claim 1 , further comprising a first signal line partially overlapping the second semiconductor layer,
wherein the second semiconductor layer comprises an opening in a closed shape, and the first signal line comprises a first switching gate electrode and a second switching gate electrode respectively overlapping a 2 nd -1 st semiconductor layer and a 2 nd -2 nd semiconductor layer which are separated by the opening.

3 . The display apparatus of claim 1 , further comprising a second signal line partially overlapping the third semiconductor layer,
wherein the second signal line comprises a first initialization gate electrode and a second initialization gate electrode respectively overlapping a 3 rd -1 st semiconductor layer and a 3 rd -2 nd semiconductor layer.

4 . The display apparatus of claim 3 , wherein the second signal line comprises a 2 nd -1 st signal line disposed under the third semiconductor layer and a 2 nd -2 nd signal line disposed over the third semiconductor layer,
the 2 nd -1 st signal line comprises a lower gate electrode in an area overlapping the third semiconductor layer, and the 2 nd -2 nd signal line comprises an upper gate electrode in an area overlapping the third semiconductor layer.

5 . The display apparatus of claim 4 , wherein at least one of the lower gate electrode and the upper gate electrode is provided as a dual gate electrode.

6 . The display apparatus of claim 1 , wherein the first semiconductor layer and the second semiconductor layer are integrally provided as a single body.

7 . The display apparatus of claim 1 , further comprising a driving transistor which controls a magnitude of a driving current flowing to the display element,
wherein the switching transistor transfers a data voltage to a source electrode of the driving transistor, the emission control transistor generates a path of the driving current between the display element, and the first initialization transistor applies an initialization voltage to a gate electrode of the driving transistor.

8 . The display apparatus of claim 1 , further comprising:
a first power voltage line; a first planarization layer covering the first power voltage line; and a second planarization layer on the first planarization layer, wherein the pixel electrode connected to the emission control transistor is disposed on the second planarization layer.

9 . A display apparatus comprising:
a substrate comprising a display area on which a display element is disposed; an emission control transistor which is disposed in the display area, comprises a first semiconductor layer, and is connected to a pixel electrode of an organic light-emitting diode; a switching transistor disposed in the display area and comprising a second semiconductor layer; a first initialization transistor disposed in the display area and comprising a third semiconductor layer; and an emission control line partially overlapping the first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer each comprise a silicon semiconductor, the third semiconductor layer comprises an oxide semiconductor, and at least one of the emission control transistor, the switching transistor, and the first initialization transistor comprises a dual gate electrode, the emission control line comprises an opening, and the dual gate electrode of the emission control transistor is provided in a first emission control gate electrode and a second emission control gate electrode which are both obtained by branching by the opening.

10 . The display apparatus of claim 9 , wherein the opening is provided as a through hole in a closed shape.

11 . A display apparatus comprising:
a substrate comprising a display area on which a display element is disposed; a driving transistor which controls a magnitude of a driving current flowing to the display element; an emission control transistor disposed in the display area and connected to a pixel electrode of an organic light-emitting diode; a switching transistor which is disposed in the display area, comprises a second semiconductor layer comprising a silicon semiconductor, and transfers a data voltage to a source electrode of the driving transistor; a first initialization transistor which is disposed in the display area, comprises a third semiconductor layer comprising an oxide semiconductor, and applies an initialization voltage to a gate electrode of the driving transistor; an emission control line partially overlapping the first semiconductor layer; and a first signal line partially overlapping the second semiconductor layer, wherein the emission control transistor and the switching transistor each comprise a dual gate electrode.

12 . The display apparatus of claim 11 , wherein the emission control line and the second semiconductor layer each comprise an opening.

13 . The display apparatus of claim 12 , wherein the dual gate electrode of the emission control transistor is provided in a first emission control gate electrode and a second emission control gate electrode which are both obtained by branching by the opening of the emission control line.

14 . The display apparatus of claim 13 , wherein the first signal line comprises a first switching gate electrode and a second switching gate electrode respectively overlapping a 2 nd -1 st semiconductor layer and a 2 nd -2 nd semiconductor layer which are separated by the opening of the second semiconductor layer.

15 . The display apparatus of claim 11 , further comprising a second signal line overlapping the third semiconductor layer in a plurality of areas,
wherein the second signal line comprises a first initialization gate electrode and a second initialization gate electrode respectively overlapping a 3 rd -1 st semiconductor layer and a 3 rd -2 nd semiconductor layer.

16 . The display apparatus of claim 15 , further comprising an upper gate electrode and a lower gate electrode respectively disposed over and under the third semiconductor layer,
wherein at least one of the upper gate electrode and the lower gate electrode is provided as a dual gate electrode.

17 . The display apparatus of claim 11 , wherein the first semiconductor layer and the second semiconductor layer are integrally provided as a single body,
the switching transistor and the emission control transistor are provided in p-channel metal-oxide semiconductor field-effect transistors, and the first initialization transistor is provided in an n-channel metal-oxide semiconductor field-effect transistor.

18 . The display apparatus of claim 11 , further comprising:
a first power voltage line; a

Assignees

• Samsung Display Co Ltd

Inventors

• Choi Jonghyun
• Kim Younjoon
• Lee Kijune

Classifications

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title