Semiconductor device

Patent metadata

Field	Value
Publication number	US-12501672-B2
Application number	US-202318127298-A
Country	US
Kind code	B2
Filing date	Mar 28, 2023
Priority date	Aug 22, 2022
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

A semiconductor device is provided. The semiconductor device includes: an active pattern extending in on a substrate; nanosheets stacked on the active pattern; a gate electrode on the active pattern and surrounding the nanosheets; a source/drain trench on the active pattern adjacent the gate electrode; and a source/drain region in the source/drain trench, The source/drain region includes: a first layer provided along a sidewall and a bottom surface of the source/drain trench, the first layer having a first n-type impurity doped therein; a second layer on the first layer in the source/drain trench, the second layer having germanium (Ge) doped therein; and a third layer filling a remaining portion of the source/drain trench on the second layer, the third layer having a second n-type impurity doped therein.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a substrate comprising an n-type metal-oxide-semiconductor field-effect transistor (NMOS) region; an active pattern extending in a first horizontal direction on the substrate; a plurality of nanosheets stacked on the active pattern and spaced apart from each other in a vertical direction; a gate electrode on the active pattern and surrounding the plurality of nanosheets, wherein the gate electrode extends in a second horizontal direction different from the first horizontal direction; a source/drain trench on the active pattern adjacent the gate electrode; and a source/drain region in the source/drain trench, wherein the source/drain region comprises:
a first layer provided along a sidewall and a bottom surface of the source/drain trench, the first layer having a first n-type impurity doped therein;
a second layer on the first layer in the source/drain trench, the second layer having germanium (Ge) doped therein; and
a third layer filling a remaining portion of the source/drain trench on the second layer, the third layer having a second n-type impurity doped therein.

2 . The semiconductor device of claim 1 , wherein the first layer continuously extends along the sidewall and the bottom surface of the source/drain trench.

3 . The semiconductor device of claim 1 , wherein each of the first layer, the second layer and the third layer overlaps an uppermost nanosheet of the plurality of nanosheets in the first horizontal direction.

4 . The semiconductor device of claim 1 , wherein the first layer is in contact with a sidewall of each of the plurality of nanosheets.

5 . The semiconductor device of claim 1 , wherein each of the first n-type impurity and the second n-type impurity is different from germanium (Ge).

6 . The semiconductor device of claim 5 , wherein the first n-type impurity comprises one of phosphorus (P), arsenic (As), antimony (Sb), or bismuth (Bi), and the second n-type impurity comprises phosphorus (P).

7 . The semiconductor device of claim 1 , further comprising a gate insulating layer between the gate electrode and the first layer between adjacent ones of the plurality of nanosheets, the gate insulating layer being in contact with the first layer.

8 . The semiconductor device of claim 1 , further comprising an inner spacer between the gate electrode and the first layer between adjacent ones of the plurality of nanosheets, the inner spacer being in contact with the first layer.

9 . The semiconductor device of claim 1 , wherein the second layer is in contact with the first layer.

10 . The semiconductor device of claim 1 , wherein the source/drain region further comprises a fourth layer between the first layer and the second layer, and
wherein the fourth layer is doped with both the first n-type impurity and germanium (Ge).

11 . The semiconductor device of claim 10 , wherein the fourth layer is in contact with a sidewall of each of the plurality of nanosheets.

12 . The semiconductor device of claim 11 , wherein at least a portion of the first layer is between the gate electrode and the fourth layer between adjacent ones of the plurality of nanosheets.

13 . A semiconductor device comprising:
a substrate comprising an n-type metal-oxide-semiconductor field-effect transistor (NMOS) region; an active pattern extending in a first horizontal direction on the substrate; a plurality of nanosheets stacked on the active pattern and spaced apart from each other in a vertical direction; a gate electrode on the active pattern and surrounding the plurality of nanosheets, wherein the gate electrode extends in a second horizontal direction different from the first horizontal direction; a source/drain trench on the active pattern adjacent the gate electrode; a source/drain region in the source/drain trench; and a gate insulating layer between the gate electrode and the source/drain region between adjacent ones of the plurality of nanosheets, the gate insulating layer being in contact with the source/drain region, wherein the source/drain region comprises:
a first layer continuously extending along a sidewall and a bottom surface of the source/drain trench, the first layer having a first n-type impurity doped therein; and
a second layer on the first layer in the source/drain trench, the second layer having germanium (Ge) doped therein.

14 . The semiconductor device of claim 13 , wherein the source/drain region further comprises a third layer on the second layer that fills a remaining portion of the source/drain trench, wherein the third layer has a second n-type impurity doped therein, and
wherein each of the first n-type impurity and the second n-type impurity is different from germanium (Ge).

15 . The semiconductor device of claim 14 , further comprising an air gap in the third layer.

16 . The semiconductor device of claim 13 , wherein each of the first layer and the second layer overlaps an uppermost nanosheet of the plurality of nanosheets in the first horizontal direction.

17 . The semiconductor device of claim 13 , wherein the source/drain region further comprises a fourth layer between the first layer and the second layer, and
wherein the fourth layer is doped with both the first n-type impurity and germanium (Ge).

18 . The semiconductor device of claim 13 , wherein a content of germanium (Ge) doped into the second layer is in a range of 3 at % (atomic percent) to 20 at %.

19 . The semiconductor device of claim 13 , wherein a thickness of the second layer is in a range of 1 nm to 5 nm.

20 . A semiconductor device comprising:
a substrate comprising an n-type metal-oxide-semiconductor field-effect transistor (NMOS) region; an active pattern extending in a first horizontal direction on the substrate; a plurality of nanosheets stacked on the active pattern and spaced apart from each other in a vertical direction; a gate electrode on the active pattern and surrounding the plurality of nanosheets, wherein the gate electrode extends in a second horizontal direction different from the first horizontal direction; a source/drain trench on the active pattern adjacent the gate electrode; a source/drain region in the source/drain trench; and a gate insulating layer between the gate electrode and the source/drain region between adjacent ones of the plurality of nanosheets, the gate insulating layer being in contact with the source/drain region, wherein the source/drain region comprises:
a first layer continuously extending along a sidewall and a bottom surface of the source/drain trench, the first layer being in contact with a sidewall of each of the plurality of nanosheets, and the first layer having a first n-type impurity doped therein;
a second layer on the first layer in the source/drain trench, the second layer being in contact with the first layer, and the second layer having germanium (Ge) doped therein; and
a third layer filling a remaining portion of the source/drain trench on the second layer, the third layer having a second n-type impurity doped therein,
wherein each of the first n-type impurity and the second n-type impurity is different from germanium (Ge), and wherein each of the first layer, the second layer and the third layer overlaps an uppermost nanosheet of the plurality of nanosheets in the first horizontal direction.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeon Yong Uk
• Kim Kyung Ho
• Kim Ki Hwan
• Moon Kang Hun
• Lee Cho Eun

Classifications

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title