Gallium nitride-based device with step-wise field plate and method making the same

Patent metadata

Field	Value
Publication number	US-12501644-B2
Application number	US-202117343153-A
Country	US
Kind code	B2
Filing date	Jun 9, 2021
Priority date	Jul 31, 2020
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

The present disclosure provides a semiconductor structure. The semiconductor structure includes a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; a gate stack disposed on the AlGaN layer; a source feature and a drain feature disposed on the AlGaN layer and interposed by the gate stack; a dielectric material layer is disposed on the gate stack; and a field plate disposed on the dielectric material layer and electrically connected to the source feature, wherein the field plate includes a step-wise structure.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
a gallium nitride (GaN) layer on a substrate and having a top surface with a plane normal direction oriented from the substrate to the GaN layer; an aluminum gallium nitride (AlGaN) layer disposed on the top surface of the GaN layer along the plane normal direction; a gate stack disposed on the AlGaN layer; a source feature and a drain feature disposed on the AlGaN layer and interposed by the gate stack; a first dielectric material layer disposed on the gate stack; a field plate disposed on the first dielectric material layer and electrically connected to the source feature, wherein the field plate includes a step-wise structure, wherein the step-wise structure includes a first segment extending horizontally along a first direction being perpendicular to the plane normal direction, a second segment extending vertically from the first segment along the plane normal direction, and a third segment extending horizontally from the second segment along the first direction, and wherein the third segment is above the first segment along the plane normal direction; a second dielectric material layer disposed on both the first dielectric material layer and the field plate; a first via on the source feature; a second via embedded in the second dielectric material layer and on the third segment of the field plate; and a metal line disposed on a topmost surface of the second dielectric material layer and above both the first and second vias along the plane normal direction and contacting both the first via and the second via, wherein the first via spans a first height along the plane normal direction, the second via spans a second height along the plane normal direction, the step-wise structure spans a third height along the plane normal direction, and the first height is greater than the sum of the second height and the third height.

2 . The semiconductor structure of claim 1 , wherein
the second via includes a bottom surface and a top surface along the plane normal direction; the third segment includes a top surface being coplanar with the bottom surface of the second via; the metal line includes a bottom surface being coplanar with the top surface of the second via; the bottom surface of the second via spans a first lateral dimension along the first direction; the top surface of the third segment spans a second lateral dimension along the first direction; the second lateral dimension is greater than the first lateral dimension; and the step-wise structure is only electrically connected to the metal line through the second via.

3 . The semiconductor structure of claim 2 , wherein
the metal line is extending along the first direction; the metal line is overlapped with the step-wise structure, the first via and the second via in a top view along the plane normal direction; and a bottom surface of the first via is below a bottom surface of the first segment along the plane normal direction.

4 . The semiconductor structure of claim 3 , wherein
the first via is extending from the topmost surface of the second dielectric material layer to the source feature along the plane normal direction.

5 . The semiconductor structure of claim 4 , wherein
the metal line is vertically distanced from the gate stack with a first dimension along the plane normal direction; the step-wise structure vertically spans a height along the plane normal direction; and a ratio of the height to the first dimension is less than 50%.

6 . The semiconductor structure of claim 1 , wherein the gate stack includes a III-V compound p-type doped layer.

7 . The semiconductor structure of claim 6 , wherein
the gate stack further includes a III-V compound n-type doped layer adjacent the III-V compound p-type doped layer; and the III-V compound n-type doped layer includes an n-type GaN layer and the III-V compound p-type doped layer includes a p-type GaN layer.

8 . The semiconductor structure of claim 1 , wherein
the first via spans between the source feature and the metal line along the plane normal direction; and the second via spans between the third segment and the metal line along plane normal direction.

9 . The semiconductor structure of claim 8 , wherein
the III-V compound p-type doped layer is doped with an impurity selected from the group consisting of magnesium, calcium, zinc, beryllium, and carbon; and the III-V compound n-type doped layer is doped with an impurity selected from the group consisting of silicon and oxygen.

10 . The semiconductor structure of claim 1 , wherein
the first via includes a bottom surface and a top surface along the plane normal direction; the first via includes a sidewall surface extending from the top surface to the bottom surface; and the sidewall surface of the first via is fully surrounded by the first and second dielectric material layers.

11 . The semiconductor structure of claim 1 , wherein the GaN layer is undoped or unintentionally doped.

12 . The semiconductor structure of claim 1 , wherein the source feature, the drain feature, and the gate stack are configured with the GaN layer and the AlGaN layer to form a high electron mobility transistor.

13 . A semiconductor structure, comprising:
a first III-V compound layer on a substrate; a second III-V compound layer on the first III-V compound layer, the second III-V compound layer being different from the first III-V compound layer in composition and further including aluminum; a gate stack on the second III-V compound layer; a source feature and a drain feature disposed on the second III-V compound layer; a first via and a second via; a field plate disposed over the gate stack and electrically connected to the source feature by way of the first via and the second via, wherein the field plate includes at least three segments with a step-wise structure, and wherein the first via is on the source feature, wherein the step-wise structure includes a first segment extending horizontally along a first direction, a second segment extending vertically from the first segment along a second direction being perpendicular to the first direction, and a third segment extending horizontally from the second segment along the first direction, wherein the second III-V compound layer is directly on the second III-V compound layer along the second direction, and wherein the third segment is above the first segment along the second direction and the second via is in contact with a topmost segment of the field plate along the second direction; and a metal line disposed above and contacting both the first via and the second via along the second direction, wherein the first via spans a first height along the second direction, the second via spans a second height along the second direction, the step-wise structure spans a third height along the second direction, and the first height is greater than the sum of the second height and the third height.

14 . The semiconductor structure of claim 13 , wherein
the first via includes a bottom surface and a top surface along the second direction; the second via includes a bottom surface and a top surface along the second direction; the metal line includes a bottom surface and a top surface along the second direction; the bottom surface of the metal line contacts the top surface of the first via and the top surface of the second via; the step-wise structure includes a top surface being coplanar with the bottom surface of the second via along the second direction; the bottom surface of the second via spans a first

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Wei
• Yang Wei-Chen
• Chang Yao-Chung
• Su Ru-Yi
• Lin Yen-Ku
• Tsou Chuan-Wei
• Tsai Chun Lin

Classifications

• H10D64/011 Primary

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10D64/111

  Field plates · CPC title

• H10D64/01

  Manufacture or treatment · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title