Multi-valued memory device based on negative transconductance using monolithic WSe2 thin film

Patent metadata

Field	Value
Publication number	US-12501604-B2
Application number	US-202217976234-A
Country	US
Kind code	B2
Filing date	Oct 28, 2022
Priority date	Oct 28, 2021
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

Disclosed are a negative transconductance device and a multi-valued memory device using the same. The negative transconductance includes a monolithic WSe 2 semiconductor thin film; a first doped layer disposed on a first area of the WSe 2 semiconductor thin film; a second doped layer disposed on a second area of the WSe 2 semiconductor thin film so as to supply holes to the second area, wherein the second area is spaced apart from the first area; a first electrode electrically connected to the first area of the WSe 2 semiconductor thin film; a second electrode electrically connected to the second area of the WSe 2 semiconductor thin film; and a third electrode for applying a gate voltage to the first area and the second area of the WSe 2 semiconductor thin film, and to a third area thereof located between the first and second areas.

First claim

What is claimed is:

1 . A negative transconductance device comprising:
a monolithic WSe 2 semiconductor thin film forming a continuous channel layer; a first chemically doped layer formed in a first area of the WSe 2 semiconductor thin film, the first doped region configured to supply electrons to the first area; a second chemically doped layer formed in a second area of the WSe 2 semiconductor thin film, the second doped region configured to supply holes to the second area, wherein the second area is spaced apart from the first area along a lateral direction of the WSe 2 semiconductor thin film; a third area of the WSe 2 semiconductor thin film disposed between the first and second areas and remaining substantially intrinsic or undoped; a first electrode electrically connected to the first area of the WSe 2 semiconductor thin film; a second electrode electrically connected to the second area of the WSe 2 semiconductor thin film; and a third electrode configured to apply a gate voltage simultaneously to the first area, the second area, and the third area to induce ambipolar carrier transport and generate negative transconductance behavior.

2 . The negative transconductance device of claim 1 ,
wherein the first chemically doped layer comprises CH 3 radicals as n-type dopants, and the second chemically doped layer comprises Au 2 Cl 6 as p-type dopants.

3 . The negative transconductance device of claim 2 ,
wherein a concentration of the CH 3 radicals in the first area is in a range of 1×10 11 cm −2 to 1×10 13 cm −2 , and wherein a concentration of the Au 2 Cl 6 in the second area is in a range of 1×10 11 cm −2 to 1×10 13 cm −2 .

4 . The negative transconductance device of claim 1 ,
wherein a poly (methyl methacrylate) (PMMA) coating layer is disposed on the third area of the WSe 2 semiconductor thin film to suppress unintentional doping and stabilize the intrinsic electrical properties of the third area.

5 . The negative transconductance device of claim 1 ,
wherein the device further comprises:
a semiconductor substrate; and
an insulating film disposed on a surface of the semiconductor substrate,
wherein the WSe 2 semiconductor thin film is supported by the insulating film, and wherein the semiconductor substrate functions as a global back gate for applying the gate voltage to the first, second, and third areas of the WSe 2 semiconductor thin film.

6 . A multi-valued memory device comprising:
a monolithic WSe 2 semiconductor thin film forming a continuous channel layer; a first chemically doped layer disposed in a first area of the WSe 2 semiconductor thin film and configured to supply electrons to the first area; a second chemically doped layer disposed in a second area of the WSe 2 semiconductor thin film and configured to supply holes to the second area, wherein the second area is laterally spaced apart from the first area; a third area of the WSe 2 semiconductor thin film disposed between the first and second areas and having an intrinsic or undoped carrier profile; a first electrode electrically connected to the first area of the WSe 2 semiconductor thin film; a second electrode electrically connected to the second area of the WSe 2 semiconductor thin film; and a third electrode configured to apply a gate voltage to the first, second, and third areas of the WSe 2 semiconductor thin film, wherein the device is configured to exhibit multiple stable current levels at the second electrode in response to different gate voltages applied to the third electrode, such that each current level represents a distinct logic state.

7 . The multi-valued memory device of claim 6 ,
wherein the first chemically doped layer includes CH 3 radicals as n-type dopants, and the second chemically doped layer includes Au 2 Cl 6 as p-type dopants.

8 . The multi-valued memory device of claim 7 ,
wherein the CH 3 radicals are present at a concentration in a range of 1×10 11 cm −2 to 1×10 13 cm −2 , and wherein the Au 2 Cl 6 is present at a concentration in a range of 1×10 11 cm −2 to 1×10 13 cm −2 .

9 . The multi-valued memory device of claim 6 ,
wherein a poly (methyl methacrylate) (PMMA) coating layer is disposed on the third area of the WSe 2 semiconductor thin film to suppress unintentional doping and stabilize the intrinsic electrical properties of the third region.

10 . The multi-valued memory device of claim 6 ,
wherein the device further comprises:
a semiconductor substrate; and
an insulating film disposed on a surface of the semiconductor substrate,
wherein the WSe 2 semiconductor thin film is supported by the insulating film, and wherein the semiconductor substrate functions as a global back gate for applying the gate voltage to the first, second, and third areas of the WSe 2 semiconductor thin film.

Assignees

• Research & Business Found Sungkyunkwan Univ

Inventors

• Lee Sungjoo
• Son Hyeonje
• Choi Haeju
• Kang Taeho
• Kang Chanwoo
• Baek Sungpyo
• Yoo Hyun Ho
• Ju Jae Hyeok

Classifications

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10P32/00

  Diffusion of dopants within, into or out of wafers, substrates or parts of devices (during formation of materials H10P14/00) · CPC title

• H10D62/80

  characterised by the materials · CPC title

• H10D48/362

  Unipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions, e.g. hot electron transistors [HET], metal base transistors [MBT], resonant tunnelling transistors [RTT], bulk barrier transistors [BBT], planar doped barrier transistors [PDBT] or charge injection transistors [CHINT] · CPC title

• H10D30/675

  Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium · CPC title