Printed circuit board via structures with reduced insertion loss distortion

Patent metadata

Field	Value
Publication number	US-12501549-B2
Application number	US-202318344511-A
Country	US
Kind code	B2
Filing date	Jun 29, 2023
Priority date	Jun 30, 2022
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

A printed circuit board (PCB) includes a plurality of stacked layers, each layer having a major plane defining a major plane of the PCB, a plurality of signal pads disposed on a signal pad layer of the PCB that is parallel to the major plane of the PCB, and a plurality of signal vias, each signal via in the plurality of signal vias having a longitudinal axis perpendicular to the major plane of the PCB, each signal via extending through the plurality of layers along the longitudinal axis, each respective signal via being electrically coupled to a respective signal pad of the plurality of signal pads, wherein at least one signal via in the plurality of signal vias includes an added capacitive structure which, along with inductance of that via, forms a corrective filter to reduce insertion loss deviation of at least one broadband signal in that via.

First claim

What is claimed is:

1 . A printed circuit board comprising:
a plurality of stacked layers, each layer having a respective major plane defining a major plane of the printed circuit board; a plurality of signal pads disposed on a signal pad layer of the printed circuit board that is parallel to the major plane of the printed circuit board; and a plurality of signal vias, each signal via in the plurality of signal vias having a longitudinal axis perpendicular to the major plane of the printed circuit board, each signal via extending through the plurality of stacked layers along the longitudinal axis, each respective signal via being electrically coupled to a respective signal pad of the plurality of signal pads; wherein at least one signal via in the plurality of signal vias includes an added capacitive structure which, along with inductance of the at least one signal via, forms a corrective filter to reduce insertion loss deviation of at least one broadband signal in the at least one signal via; wherein the added capacitive structure comprises a plurality of additional pads, each additional pad extending from the respective signal via parallel to the major plane of the printed circuit board without coupling conductively to any other portion of the printed circuit board; wherein a capacitance of a respective capacitive element formed by each additional pad is tuned by modifying size, shape, and spacing of that additional pad relative other metallic elements of the printed circuit board; and wherein positions of the additional pads disposed along the respective signal via are selected based on a range of wavelengths of the at least one broadband signal transmitted through the respective signal via to adjust a constructive signal interference caused by signal reflections between any two of the additional pads.

2 . The printed circuit board of claim 1 , wherein each respective additional pad is formed in a respective conductive layer of the plurality of stacked layers of the printed circuit board.

3 . The printed circuit board of claim 1 , wherein the constructive signal interference increases signal magnitude of selected portions of the at least one broadband signal to reduce the insertion loss deviation of the at least one broadband signal.

4 . The printed circuit board of claim 3 , wherein magnitude of the constructive signal interference of the at least one broadband signal is adjustable by modifying a respective position of a respective additional pad based on the range of wavelengths of the at least one broadband signal.

5 . The printed circuit board of claim 1 , wherein each respective additional pad of at least one signal via is separated from at least one stacked layer of the printed circuit board by a via anti-pad.

6 . The printed circuit board of claim 1 , wherein the plurality of signal pads comprises a plurality of differential signal pad pairs, wherein each differential signal pad pair in the plurality of differential signal pad pairs comprises:
a positive signal pad; and a negative signal pad.

7 . The printed circuit board of claim 6 , wherein the plurality of signal vias comprises a plurality of signal via pairs, each signal via pair including a positive signal via and a negative signal via, wherein each via from among the positive signal via and the negative signal via includes a corresponding additional pad, each of the corresponding additional pad of each via from among the positive signal via and the negative signal via being separated from at least one stacked layer of the printed circuit board by a plurality of via anti-pads.

8 . The printed circuit board of claim 7 , wherein:
the positive signal pad of at least one of the plurality of differential signal pad pairs is electrically coupled to the positive signal via of at least one of the plurality of signal via pairs; and the negative signal pad of at least one of the plurality of differential signal pad pairs is electrically coupled to the negative signal via of at least one of the plurality of signal via pairs.

9 . The printed circuit board of claim 1 , wherein the signal pad layer is a surface layer of the printed circuit board.

10 . The printed circuit board of claim 1 , wherein a respective one of the plurality of signal pads is disposed on a respective internal layer, parallel to the major plane, of the printed circuit board.

11 . A method for fabricating a printed circuit board, the method comprising:
stacking a plurality of printed circuit board layers, each printed circuit board layer having a respective major plane parallel to a major plane of the printed circuit board; forming a plurality of signal pads disposed on a signal pad layer of the printed circuit board that is parallel to the major plane of the printed circuit board; electrically coupling a plurality of signal vias to each of the plurality of signal pads, each respective signal via in the plurality of signal vias having a longitudinal axis perpendicular to the major plane of the printed circuit board, each signal via extending through the plurality of printed circuit board layers along the longitudinal axis, each respective signal via being electrically coupled to a respective signal pad of the plurality of signal pads; and providing an added capacitive structure in at least one signal via in the plurality of signal vias, which, along with inductance of the at least one signal via, forms a corrective filter to reduce insertion loss deviation of at least one broadband signal in the at least one signal via; wherein the added capacitive structure comprises a plurality of additional pads, each additional pad extending from the respective signal via parallel to the major plane of the printed circuit board without coupling conductively to any other portion of the printed circuit board; wherein a capacitance of a respective capacitive element formed by each additional pad is tuned by modifying size, shape, and spacing of that additional pad relative other metallic elements of the printed circuit board; and wherein positions of the additional pads disposed along the respective signal via are selected based on a range of wavelengths of the at least one broadband signal transmitted through the respective signal via to adjust a constructive signal interference caused by signal reflections between any two of the additional pads.

12 . The method for fabricating a printed circuit board according to claim 11 , further comprising forming each respective additional pad in a respective conductive layer of the plurality of printed circuit board layers of the printed circuit board.

13 . The method for fabricating a printed circuit board according to claim 11 , wherein the constructive signal interference that-increases signal magnitude of selected portions of the at least one broadband signal to reduce the insertion loss deviation of the at least one broadband signal.

14 . The method for fabricating a printed circuit board according to claim 13 , further comprising adjusting the constructive signal interference of the at least one broadband signal by modifying a respective position of a respective additional pad based on the range of wavelengths of the at least one broadband signal.

15 . The method for fabricating a printed circuit board according to claim 14 , wherein modifying a respective position of the respective additional pad to adjust the constructive signal interference caused by the signal reflections comprises:
determining whether an insertion loss deviation target has been achieved by including the respective additional pad in a respective printed c

Assignees

• Marvell Israel Misl Ltd

Inventors

• Ben Artsi Liav
• Kutscher Noam

Classifications

• H05K2201/096

  Vertically aligned vias, holes or stacked vias · CPC title

• H05K3/429

  Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers · CPC title

• H05K1/0233

  Filters, inductors or a magnetic substance · CPC title

• H05K1/116

  Lands, clearance holes or other lay-out details concerning the surrounding of a via · CPC title

• H05K1/0222

  for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence · CPC title