Transmission apparatus and method, receiving apparatus and method for latency reduction using FEC packets at MAC layer

US12500692B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12500692-B2
Application numberUS-201917263563-A
CountryUS
Kind codeB2
Filing dateAug 1, 2019
Priority dateAug 3, 2018
Publication dateDec 16, 2025
Grant dateDec 16, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A transmission apparatus for use in a communication system comprises MAC layer processing circuitry and PHY layer processing circuitry. The MAC layer processing circuitry is configured to encode, on a MAC layer, N data units, each comprising payload data, into M parity units, each comprising parity data allowing the reconstruction of one or more erroneous data units among said N data units in a receiver apparatus, according to a parity rule, the N data units and the corresponding M parity units representing a parity block, and to form a MAC layer data stream from the data units and the parity units of the parity block. The PHY layer processing circuitry is configured to encode, on a PHY layer, bits of the MAC layer data stream into codewords of a code and to form a PHY layer data stream from the codewords.

First claim

Opening claim text (preview).

The invention claimed is: 1 . A transmission apparatus for use in a communication system, the transmission apparatus comprising: MAC layer processing circuitry configured to: encode N data units on a MAC layer into M parity units according to a parity rule, wherein N is different than M, each data unit of the N data units comprises payload data, each parity unit of the M parity units comprises parity data allowing a reconstruction of one or more erroneous data units among the N data units in a receiver apparatus, and a parity block is represented by the N data units followed by the M parity units; and form a MAC layer data stream from the N data units and the M parity units of the parity block; and PHY layer processing circuitry configured to: encode, on a PHY layer, bits of the MAC layer data stream into codewords of a code; and form a PHY layer data stream from the codewords, wherein each data unit, of the N data units, includes: a data header comprising one or more of information about a type of data unit, transmission apparatus and receiving apparatus address duration information indicating duration of the data unit and sequence number of the data unit, a payload portion comprising the payload data including one or more of user data, management data and control data, and a frame check sequence comprising a checksum over the data header and the payload portion of the data unit. 2 . The transmission apparatus as claimed in claim 1 , wherein the MAC layer processing circuitry is further configured to pad the N data units by padding data to have a same length before encoding them into the M parity data units. 3 . The transmission apparatus as claimed in claim 2 , wherein the MAC layer processing circuitry is further configured to interleave the N data units and the M parity units of the parity block and to form the MAC layer data stream from the interleaved data units and parity units. 4 . The transmission apparatus as claimed in claim 1 , wherein the MAC layer processing circuitry is further configured to allocate the N data units and the M parity units of the MAC layer data stream to different PHY layer resources. 5 . The transmission apparatus as claimed in claim 1 , wherein the MAC layer processing circuitry is further configured to apply binary encoding or non-binary encoding to the N data units to generate the M parity units. 6 . The transmission apparatus as claimed in claim 1 , wherein a parity unit comprises: a parity header including one or more of: an identifier identifying the parity unit, information indicating a length of the parity unit, a length of the aggregate N data units, or a length of the parity block, transmission apparatus and receiving apparatus address, parity information indicating the applied parity rule, and parity sequence information indicating an index of the parity unit, a parity payload portion comprising the parity data, and a parity frame check sequence comprising a checksum over the parity header and the parity payload portion of the parity unit. 7 . The transmission apparatus as claimed in claim 1 , wherein the MAC layer processing circuitry is further configured to arrange a delimiter between two subsequent data units, between two subsequent parity units, or between two subsequent parity blocks. 8 . The transmission apparatus as claimed in claim 7 , wherein the MAC layer processing circuitry is further configured to add information into the delimiters indicating whether a subsequent unit is a data unit, whether the subsequent unit is a parity unit, or whether the subsequent unit is a beginning of a new parity block. 9 . The transmission apparatus as claimed in claim 1 wherein the transmission apparatus is configured to agree with the receiving apparatus or inform the receiving apparatus on the parity rule, numbers of N and M and an interleaver configuration or to determine them by evaluating capabilities of the receiving apparatus. 10 . A transmission method for use in a communication system, the transmission method comprising: performing a MAC layer processing including: encoding N data units on a MAC layer into M parity units according to a parity rule, wherein N is different than M, each data unit of the N data units comprises payload data, each parity unit of the M parity units comprises parity data allowing a reconstruction of one or more erroneous data units among the N data units in a receiver apparatus, and a parity block represented by the N data units followed by the M parity units; and forming a MAC layer data stream from the N data units and the M parity units of the parity block; and performing a PHY layer processing including: encoding, on a PHY layer, bits of the MAC layer data stream into codewords of a code; and forming a PHY layer data stream from the codewords, wherein each data unit, of the N data units, includes: a data header comprising one or more of information about a type of data unit, transmission apparatus and receiving apparatus address, duration information indicating duration of the data unit and sequence number of the data unit, a payload portion comprising the payload data including one or more of user data management data and control data, and a frame check sequence comprising a checksum over the data header and the payload portion of the data unit. 11 . A receiving apparatus for use in a communication system, the receiving apparatus comprising: PHY layer processing circuitry configured to: derive codewords of a code from a received PHY layer data stream; and decode, on a PHY layer, the codewords into bits of a MAC layer data stream; and MAC layer processing circuitry configured to: derive N data units from the MAC layer data stream to detect erasures in the N data units, wherein N is different than M, each data unit of the N data units comprises payload data and corresponds to a parity unit of M parity units, each parity unit of the M parity units comprises parity data, and a parity block is represented by the N data units followed by the M parity units; and reconstruct, on a MAC layer and according to a parity rule, one or more data units by use of the correctly received parity units in a case that an erasure is detected in one or more data units, wherein each data unit, of the N data units, includes: a data header comprising one or more of information about a type of data unit, transmission apparatus and receiving apparatus address, duration information indicating duration of the data unit and sequence number of the data unit, a payload portion comprising the payload data including one or more of user data, management data and control data, and a frame check sequence comprising a checksum over the data header and the payload portion of the data unit. 12 . The receiving apparatus as claimed in claim 11 , wherein the MAC layer processing circuitry is further configured to pad error-free data units by padding data to have a same length before reconstructing an erroneous data unit and to remove the padding data from the error-free data units after the reconstruction of the erroneous data unit. 13 . The receiving apparatus as claimed in claim 11 , wherein the MAC layer processing circuitry is further configured to deallocate the N data units and the M parity units from PHY layer resources onto the MAC layer data stream. 14 . The receiving apparatus as claimed in claim 11 , wherein the MAC layer processing circuitry is further configured to apply binary decoding or non-binary decoding to reconstruct an erroneous data unit. 15 . The receiving apparatus as claimed

Assignees

Inventors

Classifications

  • the resource being a scrambling code · CPC title

  • H04L1/0041Primary

    Arrangements at the transmitter end · CPC title

  • Transmission or retransmission of more than one copy of a message · CPC title

  • List acknowledgements, i.e. the acknowledgement message consisting of a list of identifiers, e.g. of sequence numbers (H04L1/1614 takes precedence) · CPC title

  • H04L1/0057Primary

    Block codes (H04L1/0061, H04L1/0064 take precedence) · CPC title

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What does patent US12500692B2 cover?
A transmission apparatus for use in a communication system comprises MAC layer processing circuitry and PHY layer processing circuitry. The MAC layer processing circuitry is configured to encode, on a MAC layer, N data units, each comprising payload data, into M parity units, each comprising parity data allowing the reconstruction of one or more erroneous data units among said N data units in a…
Who is the assignee on this patent?
Sony Corp
What technology area does this patent fall under?
Primary CPC classification H04L1/0041. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 16 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).