Memory device and method for operating the same

Patent metadata

Field	Value
Publication number	US-12499941-B2
Application number	US-202418409760-A
Country	US
Kind code	B2
Filing date	Jan 10, 2024
Priority date	Oct 25, 2021
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

A memory device includes a first chip, a second chip and a processor. The second chip is coupled to the first chip at a first node. The second chip includes a first capacitor and a first variable resistor. The first capacitor is coupled to the first node. The first variable resistor is coupled in series with the first capacitor. The processor is coupled to the first node, and is configured to perform a first read operation to the first chip via the first node. A method for operating a memory device is also disclosed herein.

First claim

What is claimed is:

1 . A memory device, comprising:
a first chip; a second chip coupled to the first chip, and comprising:
a first capacitor; and
a first variable resistor coupled in series with the first capacitor; and
a processor coupled to the first chip and configured to control the first variable resistor.

2 . The memory device of claim 1 , wherein the first variable resistor has a first resistance when the processor performs a first read operation to the first chip, and has a second resistance lower than the first resistance when the processor performs a second read operation to the second chip.

3 . The memory device of claim 2 , wherein the processor is further configured to increase a resistance of the first variable resistor in response to the processor performing the first read operation.

4 . The memory device of claim 3 , wherein the processor is further configured to decrease the resistance of the first variable resistor in response to the processor performing the second read operation.

5 . The memory device of claim 1 , wherein the first chip comprises:
a second capacitor; and a second variable resistor coupled in series with the second capacitor, wherein the processor is further configured to increase a resistance of the second variable resistor when the processor performs a first read operation to the second chip.

6 . The memory device of claim 5 , wherein the processor is further configured to decrease a resistance of the second variable resistor when the processor performs a second read operation to the first chip.

7 . The memory device of claim 1 , wherein the first capacitor is coupled between the first variable resistor and a ground, and
the first variable resistor is coupled between the first capacitor and the processor.

8 . The memory device of claim 1 , wherein the first chip comprises:
a second capacitor coupled to a ground; and a second variable resistor coupled between the second capacitor and the processor.

9 . The memory device of claim 1 , wherein the first capacitor is coupled between the processor and the first variable resistor, and
the first variable resistor is coupled between the first capacitor and a ground.

10 . The memory device of claim 1 , wherein the first chip comprises:
a second capacitor coupled to the processor; and a second variable resistor coupled between the second capacitor and a ground.

11 . A method for operating a memory device, comprising:
adjusting a first chip to a first resistance; after the first chip is adjusted to the first resistance, writing first data stored in a second chip into a processor; and after the first data is written into the processor, adjusting the first chip to a second resistance lower than the first resistance.

12 . The method of claim 11 , further comprising:
after the first chip is adjusted to the second resistance, writing second data stored in the first chip into the processor.

13 . The method of claim 12 , further comprising:
adjusting each of the first chip and the second chip to the second resistance; and after each of the first chip and the second chip is adjusted to the second resistance, writing third data stored in the processor into each of the first chip and the second chip.

14 . The method of claim 12 , further comprising:
adjusting the second chip to the first resistance when the second data is written into the processor.

15 . The method of claim 14 , further comprising:
adjusting the second chip to the second resistance when the first data is written into the processor.

16 . The method of claim 11 , wherein adjusting the first chip comprises:
generating a first control signal by the processor, in response to writing the first data into the processor; and receiving the first control signal by a first variable resistor in the first chip, to increase a resistance of the first variable resistor to the first resistance.

17 . A memory device, comprising:
a first chip configured to store first data; a second chip coupled to the first chip; and a processor configured to increase a resistance of the second chip and decrease a resistance of the first chip in response to reading the first data, wherein the second chip is configured to store second data, and the processor is further configured to read the second data, and configured to increase the resistance of the first chip in response to reading the second data.

18 . The memory device of claim 17 , wherein the second chip comprises:
a first variable resistor configured to be controlled by the processor; and a first capacitor coupled in series with the first variable resistor, wherein the first capacitor and the first variable resistor are coupled between the processor and a ground.

19 . The memory device of claim 18 , wherein the first chip comprises:
a second variable resistor configured to be controlled by the processor; and a second capacitor coupled in series with the second variable resistor, wherein the second capacitor and the second variable resistor are coupled between the first variable resistor and the ground.

Assignees

• Nanya Technology Corp

Inventors

• Hung Kuo-Chiang

Classifications

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C13/0038

  Power supply circuits · CPC title

• H01C10/16

  including plural resistive elements · CPC title

• G11C7/1057

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title