Organic light emitting diode (OLED) display substrate increasing pixel density by slightly changing size of pixel circuit, display panel, and display device

Patent metadata

Field	Value
Publication number	US-12499840-B2
Application number	US-202117997125-A
Country	US
Kind code	B2
Filing date	Oct 29, 2021
Priority date	Oct 29, 2021
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

A display substrate includes a plurality of pixel circuits arranged in an array and a plurality of light emitting devices provided on a substrate, and at least one pixel circuit is connected to a corresponding light emitting device through a conductive structure. At least some of the pixel circuits in at least one column include a first pixel circuit and a second pixel circuit arranged on a side of the first pixel circuit away from the substrate, orthographic projections of the second pixel circuit and the first pixel circuit on the substrate partially overlap to form an overlapping portion defining a first pattern, and an orthographic projection of a conductive structure of the first pixel circuit on the substrate, the first pattern, and an orthographic projection of a conductive structure of the second pixel circuit on the substrate are sequentially arranged in a first direction.

First claim

What is claimed is:

1 . A display substrate, comprising:
a substrate; and a plurality of pixel circuits and a plurality of light emitting devices provided on the substrate, wherein the plurality of pixel circuits are arranged in an array, and at least one pixel circuit is connected to a corresponding light emitting device through a conductive structure, wherein at least some of pixel circuits in at least one column comprise at least one first pixel circuit and at least one second pixel circuit forming at least one group, and each group of the at least one group is formed of a first pixel circuit and a second pixel circuit corresponding to the first pixel circuit, wherein in each group formed of the first pixel circuit and the second pixel circuit, the second pixel circuit is arranged on a side of the first pixel circuit away from the substrate, an orthographic projection of the second pixel circuit on the substrate partially overlaps with an orthographic projection of the first pixel circuit on the substrate, wherein an overlapping portion between the orthographic projection of the second pixel circuit on the substrate and the orthographic projection of the first pixel circuit on the substrate defines a first pattern, and an orthographic projection of a conductive structure of the first pixel circuit on the substrate, the overlapping portion defining the first pattern, and an orthographic projection of a conductive structure of the second pixel circuit on the substrate are sequentially arranged in a first direction.

2 . The display substrate according to claim 1 , wherein
the at least one pixel circuit comprises an input sub-circuit, a driving sub-circuit and a light-emission control sub-circuit, the input sub-circuit and the light-emission control sub-circuit are connected to the driving sub-circuit, the input sub-circuit is further connected to a scan signal line and a data voltage signal line, and the light-emission control sub-circuit is further connected to a first power line, a light-emission control line and the conductive structure; the input sub-circuit is configured to transmit a data voltage signal of the data voltage signal line to the driving sub-circuit in response to a control of the scan signal line; the light-emission control sub-circuit is configured to transmit a first voltage signal of the first power line to the driving sub-circuit and transmit a driving current provided by the driving sub-circuit to the conductive structure, in response to a control of the light-emission control line; and the driving sub-circuit is configured to provide the driving current according to the data voltage signal and the first voltage signal; and wherein the driving sub-circuit and the light-emission control sub-circuit of at least one first pixel circuit are sequentially arranged in the first direction; the driving sub-circuit and the light-emission control sub-circuit of at least one second pixel circuit are sequentially arranged in a second direction; and the first direction is the same as an extension direction of the data voltage signal line, and the second direction is opposite to the first direction.

3 . The display substrate according to claim 2 , wherein the at least one pixel circuit further comprises a reset sub-circuit, wherein the reset sub-circuit is connected to the driving sub-circuit, a reference signal line and a reset signal line;
wherein the reset sub-circuit is configured to transmit a reference signal of the reference signal line to the driving sub-circuit in response to a control of the reset signal line; and wherein the reset sub-circuit of the at least one pixel circuit is located on a side of the driving sub-circuit away from the light-emission control sub-circuit.

4 . The display substrate according to claim 3 , wherein the at least one pixel circuit comprises a semiconductor layer, a first gate insulating layer, a first gate layer, an interlayer insulating layer and a first metal layer sequentially arranged in a direction away from the substrate; and the reset signal line, the scan signal line and the light-emission control line are located in the first gate layer; and
wherein the reset signal line, the scan signal line and the light-emission control line connected to the first pixel circuit are sequentially arranged in the first direction, and the reset signal line, the scan signal line and the light-emission control line connected to the second pixel circuit are sequentially arranged in the second direction.

5 . The display substrate according to claim 4 , wherein the conductive structure in the first pixel circuit comprises a first connection portion and a second connection portion located on a side of the first connection portion away from the substrate, the first connection portion is connected to the light-emission control sub-circuit, and the second connection portion is connected to the light emitting device; and
wherein the first connection portion is arranged in the same layer as the first metal layer in the second pixel circuit, or the first connection portion is arranged in the same layer as the semiconductor layer in the second pixel circuit.

6 . The display substrate according to claim 4 , wherein the data voltage signal line is located in the first metal layer, the input sub-circuit comprises an input transistor, a first electrode connection portion of the input transistor is located in the semiconductor layer, a gate electrode of the input transistor is formed as an integral structure with the scan signal line, the first electrode connection portion of the input transistor is connected to a first electrode of the input transistor through a first via hole, the first electrode of the input transistor is connected to the data voltage signal line, and a second electrode of the input transistor is connected to the driving sub-circuit; and
wherein the first via hole penetrates the first gate insulating layer and the interlayer insulating layer, and the first via hole is located between the scan signal line and the reset signal line.

7 . The display substrate according to claim 4 , wherein the driving sub-circuit comprises a driving transistor and a storage capacitor;
wherein a gate electrode of the driving transistor is connected to the reset sub-circuit and a first plate of the storage capacitor, a first electrode of the driving transistor is connected to the input sub-circuit, a second electrode of the driving transistor is connected to the light-emission control sub-circuit, and a second plate of the storage capacitor is connected to the light-emission control sub-circuit and the first power line; and wherein the driving transistor and the storage capacitor are located between the light-emission control line and the scan signal line.

8 . The display substrate according to claim 7 , wherein the at least one pixel circuit further comprises a second gate layer provided on a side of the first gate layer and the interlayer insulating layer away from the substrate, and a second gate insulating layer is provided between the first gate layer and the second gate layer;
wherein the first plate of the storage capacitor is formed as an integral structure with the gate electrode of the driving transistor, and the second plate of the storage capacitor is located in the second gate layer; and wherein the second plate of the storage capacitor is connected to the first power line through a second via hole penetrating the interlayer insulating layer.

9 . The display substrate according to claim 7 , wherein the first plate of the storage capacitor is connected to the reset sub-circuit through a conductive portion located in the first metal layer; and
wherein the first plate of the stor

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Zhang Chenyang
• Zhang Zhenyu
• Wang Hongrun
• Li Haixu
• Li Fuqiang

Classifications

• G09G2300/0443

  with several sub-pixels for the same colour in a pixel, not specifically used to display gradations (G09G3/364 takes precedence) · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title