Shift register, gate driving circuit, panel, control method and driving apparatus

Patent metadata

Field	Value
Publication number	US-12499802-B2
Application number	US-202418912630-A
Country	US
Kind code	B2
Filing date	Oct 11, 2024
Priority date	May 27, 2024
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

Embodiments of the present application provides a shift register, a gate driving circuit, a panel, a control method and a driving apparatus, the shift register comprises: an output control module, a full screen reset module, a cascade output module and an output module; the output control module is configured to turn on when there is no electrostatic discharge in the shift register so that the first gate signal output terminal outputs a target signal; the cascade output module is configured to provide the first voltage signal or the second voltage signal to the second gate signal output terminal when there is electrostatic discharge in the shift register.

First claim

What is claimed is:

1 . A shift register, comprising:
an output control module, a full screen reset module, a cascade output module and an output module that are electrically connected, wherein the output control module is configured to turn on when there is no electrostatic discharge in the shift register to transmit a signal of a first node to a second node so that a first gate signal output terminal outputs a target signal configured to drive a current row of display element to display or not display, or the output control module is configured to turn off when there is electrostatic discharge in the shift register; the full screen reset module is configured to reset the potential of the second node and the potential of the first gate signal output terminal when there is electrostatic discharge in the shift register, the first gate signal output terminal not outputting any signal when the output control module is turned off and the second node and the first gate signal output terminal are in a reset state; the cascade output module is configured to provide a first voltage signal to a second gate signal output terminal under the control of a first driving signal when there is electrostatic discharge in the shift register, or the cascade output module is configured to provide a second voltage signal to a second gate signal output terminal under the control of a second driving signal, a signal output by the second gate signal output terminal being configured to drive a next row of display element to display or not display; the output module is configured to provide a signal of a first clock signal terminal to the first gate signal output terminal under the control of a signal of the second node, or the output module is configured to provide a signal of a first reference voltage terminal to the first gate signal output terminal under the control of a signal of a third node, or the output module is configured not to output any signal when the output control module is turned off.

2 . The shift register of claim 1 , further comprising a node control module, a node charging module, a scanning control module and a reset module that are electrically connected, wherein
the node control module is configured to control a signal of the second node or the third node to control the level of the signal of the second node or the third node to be opposite; the node charging module comprises a first control terminal and is configured to provide a signal of a input node to the third node under the control of a signal of the first control terminal; the scanning control module is configured to provide a signal of a forward scanning control terminal to the input node under the control of a signal of a forward scanning input signal terminal, or the scanning control module is configured to provide a signal of a reverse scanning control signal terminal to the input node under the control of a signal of a reverse scanning input signal terminal; the reset module comprises a reset control terminal and configured to reset the potential of the first node under the control of the reset control terminal, and provide a signal of a second reference voltage terminal to the third node.

3 . The shift register of claim 2 , wherein the node control module comprises an eighth transistor, a ninth transistor and a tenth transistor,
a gate of the eighth transistor being connected with the third node, a first electrode of the eighth transistor being connected with the node charging module and the first node respectively, and a second electrode of the eighth transistor being connected with the first reference voltage terminal, a gate of the ninth transistor being connected with the input node, a first electrode of the ninth transistor being connected with the first reference voltage terminal, and a second electrode of the ninth transistor being connected with the gate of the eighth transistor and the third node respectively, a gate of the tenth transistor being connected with the first node, a first electrode of the tenth transistor being connected with the first reference voltage terminal, and a second electrode of the tenth transistor being connected with the third node.

4 . The shift register of claim 2 , wherein the node charging module comprises an eleventh transistor,
a gate of the eleventh transistor being connected with the first control terminal, a first electrode of the eleventh transistor being connected with the first node, and a second electrode of the eleventh transistor being connected with the input node.

5 . The shift register of claim 2 , wherein the scan control module comprises a twelfth transistor and a thirteenth transistor,
a gate of the twelfth transistor being connected with the forward scanning input signal terminal, a first electrode of the twelfth transistor being connected with the forward scanning control signal terminal, and a second electrode of the twelfth transistor being connected with the input node, a gate of the thirteenth transistor being connected with the reverse scanning input signal terminal, a first electrode of the thirteenth transistor being connected with the reverse scanning control signal terminal, and a second electrode of the thirteenth transistor being connected with the input node.

6 . The shift register of claim 2 , wherein the reset module comprises a fourteenth transistor and a fifteenth transistor,
a gate of the fourteenth transistor being connected with the reset control terminal, a first electrode of the fourteenth transistor being connected with the first node, and a second electrode of the fourteenth transistor being connected with the input node, a gate of the fifteenth transistor being connected with the gate of the fourteenth transistor and the reset control terminal respectively, a first electrode of the fifteenth transistor being connected with the third node and a second electrode of the fifteenth transistor being connected with the second reference voltage terminal.

7 . The shift register of claim 1 , further comprising a discharge module and a reset control module that are electrically connected, wherein
the discharge module comprises a discharge control terminal and is configured to provide a signal of a first reference voltage terminal to the first node and the third node respectively, and provide a signal of a second reference voltage terminal or a signal of the discharge control terminal to the first gate signal output terminal under the control of the discharge control terminal; the reset control module is configured to provide a signal of a second clock signal terminal to the reset control terminal under the control of a signal of a forward scanning control signal terminal, or the reset control module is configured to provide a signal of a third clock signal terminal to the reset control terminal under the control of a signal of a reverse scanning control signal terminal.

8 . The shift register of claim 7 , wherein the discharge module comprises a sixteenth transistor, a seventeenth transistor and an eighteenth transistor,
a gate of the sixteenth transistor being connected with the discharge control terminal, a first electrode of the sixteenth transistor being connected with the first node, and a second electrode of the sixteenth transistor being connected with the first reference voltage terminal, a gate of the seventeenth transistor being connected with the discharge control terminal, a first electrode of the seventeenth transistor being connected with the third node, and a second electrode of the seventeenth transistor being connected with the first reference voltage terminal, a gate of the eighteenth transistor being connected with the discharge control terminal, a first electrode of the eigh

Assignees

• Xiamen Tianma Micro Electronics Co Ltd

Inventors

• Chen Huiying
• Zou Zongjun
• Wu Changzhi
• Xu Yumin

Classifications

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G3/32 Primary

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title

• G09G2330/04

  Display protection · CPC title