System and method for cache pooling and efficient usage and I/O transfer in disaggregated and multi-processor architectures via processor interconnect

Patent metadata

Field	Value
Publication number	US-12499046-B2
Application number	US-202118293354-A
Country	US
Kind code	B2
Filing date	Oct 14, 2021
Priority date	Aug 5, 2021
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

A method of cache pooling is presented where the method includes determining whether a cache of a primary processor assigned to execute an application has insufficient storage space to allot for the application, select at least one alternative processor from a list of alternative processors based on a cache availability or metric for each processor in the list of alternative processors, configuring the primary processor and the selected at least one alternative processor for mutual cache visibility, and configure routing of traffic to the application to be divided between the primary processor cache and the selected at least one alternative processor cache.

First claim

What is claimed is:

1 . A method of cache pooling from a pool of processors connected to a top of rack (ToR) switch at a disaggregated data center, the method comprising:
receiving an application identifier for an application to be executed by a primary processor from the pool of processors and a processor identifier of the primary processor assigned to execute the application; storing the application identifier and the processor identifier of the primary processor as an entry in a cache coordinator (CACO) table associated with the ToR switch; determining whether a primary processor cache of the primary processor assigned to execute the application has insufficient cache storage space to allot for the application; selecting at least one alternative processor from the pool of processors based on a cache availability or metric for each processor from a list of alternative processors to share cache storage space with the primary processor for executing the application; storing respective processor identifier of the at least one alternative processor selected to share cache storage space with the primary processor in the entry of the CACO table; configuring the primary processor and the selected at least one alternative processor for mutual cache visibility; and configuring routing of traffic to the application to be divided between the primary processor cache and the selected at least one alternative processor cache based on the entry of the CACO table.

2 . The method of claim 1 , further comprising:
retrieving the list of alternative processors from the entry for the application in the CACO table.

3 . The method of claim 1 , further comprising:
determining an amount of cache storage space to utilized for the selected at least one alternative processor; and isolating the amount of cache storage space for the application at the selected at least one alternative processor.

4 . The method of claim 1 , further comprising:
determining the application and the primary processor for the application to handle a received data to be processed.

5 . The method of claim 4 , wherein the received data is an Input/Output (I/O) packet or a data received from a solid state drive via PCIe.

6 . The method of claim 1 , further comprising:
receiving a priority of the application; and storing the priority of the application in the entry for the application in the CACO table.

7 . The method of claim 1 , further comprising:
configuring the primary processor and the selected at least one alternative processor for mutual visibility.

8 . The method of claim 1 , further comprising:
configuring routing of traffic for the application to be divided between the primary processor cache and cache of the selected at least one alternative processor.

9 . The method of claim 1 , wherein the primary processor cache is any one or more of a static random access memory, a dynamic random access memory, or a high bandwidth memory.

10 . The method of claim 1 , further comprising:
placing data in main memory where additional cache storage space is not available in the list of alternative processors.

11 . The method of claim 1 , wherein the metric includes any one or more of bandwidth, a number of running applications on alternative processors, or relative priorities of applications on different alternative processors.

12 . An electronic device for cache pooling from a pool of processors connected to a top of rack (ToR) switch at a disaggregated data center comprising:
a machine-readable storage medium having stored therein a cache coordinator (CACO); and a processor coupled to the machine-readable storage medium, the processor to execute the (CACO) to perform operations to:
receive an application identifier for an application to be executed by a primary processor from the pool of processors and a processor identifier of the primary processor assigned to execute the application;
store the application identifier and the processor identifier of the primary processor as an entry in a (CACO) table associated with the ToR switch;
determine whether a primary processor cache of the primary processor assigned to execute the application has insufficient cache storage space to allot for the application;
select at least one alternative processor from the pool of processors based on a cache availability or metric for each processor from a list of alternative processors to share cache storage space with the primary processor for executing the application;
store respective processor identifier of the at least one alternative processor selected to share cache storage space with the primary processor in the entry of the CACO table;
configure the primary processor and the selected at least one alternative processor for mutual cache visibility; and
configure routing of traffic to the application to be divided between the primary processor cache and the selected at least one alternative processor cache based on the entry of the CACO table.

13 . The electronic device of claim 12 , wherein the operations further to:
retrieve the list of alternative processors from the entry for the application in the CACO table.

14 . The electronic device of claim 12 , wherein the operations further to:
determine an amount of cache storage space to utilized for the selected at least one alternative processor; and isolate the amount of cache storage space for the application at the selected at least one alternative processor.

15 . The electronic device of claim 12 , wherein the operations further to:
determine primary processor for the application to handle a received data to be processed.

16 . The electronic device of claim 15 , wherein the received data is an Input/Output (I/O) packet or a data received from a solid state drive via PCIe.

17 . The electronic device of claim 12 , wherein the operations further to:
receive a priority of the application; and store the priority of the application in the entry for the application in the CACO table.

18 . The electronic device of claim 12 , wherein the operations further to:
configure the primary processor and the selected at least one alternative processor for mutual visibility.

Assignees

• Ericsson Telefon Ab L M
• Telefonakiebolaget Lm Ericsson Publ

Inventors

• Roozbeh Amir
• Padala Chakri
• Farshin Alireza

Classifications

• G06F2212/1048

  Scalability · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F12/0813

  with a network or matrix configuration · CPC title

• G06F12/0842

  for multiprocessing or multitasking · CPC title

• G06F12/0831

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title