Latency aware dynamic memory map

Patent metadata

Field	Value
Publication number	US-12499038-B2
Application number	US-202318496675-A
Country	US
Kind code	B2
Filing date	Oct 27, 2023
Priority date	Oct 27, 2023
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

An edge network includes an information handling system configured to manage a shared memory, and a client device. A series of edge systems each include a portion of the shared memory. The information handling system determines that the client device is bottlenecked in processing a service, locks data associated with the service in the shared memory of a first edge system, permits a second edge system to access the first data, and directs the second edge system to process the service.

First claim

What is claimed is:

1 . An edge network, comprising:
an information handling system configured to manage a shared memory; a client device including a client Smart Data Accelerator Interface (SDXI) agent; and a plurality of edge systems, each edge system including a portion of the shared memory and an edge system SDXI agent; wherein the information handling system is further configured to determine that the client device is bottlenecked in processing a first service, to direct a first edge system SDXI agent to lock first data associated with the first service in the shared memory of a first edge system, to direct a second edge system SDXI agent to permit a second edge system to access the first data, and to direct the second edge system to process the first service; and wherein the information handling system is further configured to determine that the client device is bottlenecked in processing a second service, to move second data associated with the second service from the shared memory of a third edge system to the shared memory of a fourth edge system, to permit the client device to access the second data in the shared memory of the fourth edge system, and to direct the client device to process the second service, wherein the fourth edge system is closer in the edge network to the client device than the third edge system.

2 . The edge network of claim 1 wherein in processing the first service, the second edge system is configured to write a result of the processing of the first service to the shared memory of the first edge system.

3 . The edge network of claim 2 , wherein the information handling system is further configured to determine that the second edge system has completed processing the first service.

4 . The edge network of claim 3 wherein, when the processing of the first service is completed, the information handling system is further configured to direct the first edge system SDXI agent to unlock the first data in the shared memory of the first edge system.

5 . The edge network of claim 1 , wherein in processing the second service, the client device is configured to write a result of the processing of the second service to the shared memory of the fourth edge system.

6 . The edge network of claim 5 , wherein the information handling system is further configured to determine that the client device has completed processing the second service.

7 . The edge network of claim 6 , wherein, when the processing of the second service is completed, the information handling system is further configured to unlock the second data in the shared memory of the fourth edge system.

8 . The edge network of claim 1 , wherein the shared memory is a Smart Data Accelerator Interface shared memory.

9 . A method, comprising:
providing, in an edge network, an information handling system configured to manage a shared memory; providing, in the edge network, a client device; providing, in the edge network, a plurality of edge systems, each edge system including a portion of the shared memory; determining, by the information handling system, that the client device is bottlenecked in processing a first service; locking first data associated with the first service in the shared memory of a first edge system; permitting a second edge system to access the first data; directing the second edge system to process the first service; determining, by the information handling system, that the client device is bottlenecked in processing a second service; moving second data associated with the second service from the shared memory of a third edge system to the shared memory of a fourth edge system, wherein the fourth edge system is closer in the edge network to the client device than the third edge system; permitting the client device to access the second data in the shared memory of the fourth edge system; and directing the client device to process the second service.

10 . The method of claim 9 wherein in processing the first service, the method further comprises writing a result of the processing of the first service to the shared memory of the first edge system.

11 . The method of claim 10 , further comprising determining that the second edge system has completed processing the first service.

12 . The method of claim 11 wherein, when the processing of the first service is completed, the method further comprises unlocking the first data in the shared memory of the first edge system.

13 . The method of claim 9 wherein in processing the second service, the method further comprises writing, by the client device, a result of the processing of the second service to the shared memory of the fourth edge system.

14 . The method of claim 13 , further comprising determining that the client device has completed processing the second service.

15 . The method of claim 14 wherein, when the processing of the second service is completed, the method further comprises unlocking the second data in the shared memory of the fourth edge system.

16 . The method of claim 9 , wherein the shared memory is a Smart Data Accelerator Interface shared memory.

Assignees

• Dell Products Lp

Inventors

• Khosrowpour Farzad
• Markow Mitchell

Classifications

• G06F9/5072

  Grid computing · CPC title

• G06F9/526

  Mutual exclusion algorithms · CPC title

• G06F9/524

  Deadlock detection or avoidance · CPC title

• G06F9/544

  Buffers; Shared memory; Pipes · CPC title

• G06F15/167

  using a common memory, e.g. mailbox · CPC title