Techniques for configuring a processor to function as multiple, separate processors in a virtualized environment

Patent metadata

Field	Value
Publication number	US-12498979-B2
Application number	US-202117164718-A
Country	US
Kind code	B2
Filing date	Feb 1, 2021
Priority date	Sep 5, 2019
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

A parallel processing unit (PPU), operating in a traditional processing environment or in a virtualized processing environment, can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

First claim

What is claimed is:

1 . A system, comprising:
one or more guest operating systems executing in a first computer system; a hypervisor that manages access by the one or more guest operating systems to a first processor in the first computer system, wherein the first processor is partitioned into a plurality of logical processors, and wherein each logical processor in the plurality of logical processors:
performs functions of the first processor, while using a fraction of a total capacity of the first processor,
is assigned exclusive use of a subset of a plurality of hardware resources included in the first processor, and
executes in functional isolation from all other logical processors;
a first interception layer executing on a second processor or on a third processor in a second computer system that is remote from the first computer system and that:
routes a request generated via a first application programming interface (API) by a software application executing on the second processor to a first available hardware resource selected from the subset of the plurality of hardware resources; and
a second interception layer executing the first processor or on a fourth processor in the first computer system that:
translates the request generated via the first API to API calls for a second API supported by a driver executing on the first processor or on the fourth processor in the first computer system,
subsequent to translating the request, transmits the request to the driver, and
routes a response to the request from the driver to the first interception layer executing on the second computer system.

2 . The system of claim 1 , wherein the first processor comprises a graphics processing unit (GPU).

3 . The system of claim 1 , wherein the first available hardware resource comprises a cache, a cluster of processing cores, a memory controller, a context switching unit, a scheduler, or a work distribution unit.

4 . The system of claim 1 , wherein a first logical processor in the plurality of logical processors is assigned exclusive use of a first percentage of the plurality of hardware resources and a second logical processor is assigned exclusive use of less than the first percentage of the plurality of hardware resources.

5 . The system of claim 1 , wherein each logical processor in the plurality of logical processors executes tasks associated with a different guest operating system included in the one or more guest operating systems.

6 . The system of claim 1 , wherein a first logical processor in the plurality of logical processors executes a first set of tasks in parallel with a second logical processor in the plurality of logical processors executing a second set of tasks.

7 . The system of claim 1 , wherein a first logical processor in the plurality of logical processors includes a plurality of processing engines, and wherein a first processing engine included in the plurality of processing engines executes a first set of processing tasks associated with a first processing context in a given time interval and a second processing engine included in the plurality of processing engines executes a second set of processing tasks associated with the first processing context in the given time interval.

8 . The system of claim 1 , wherein a first logical processor in the plurality of logical processors includes a plurality of processing engines, wherein a first processing context executing within a first processing engine included in the plurality of processing engines is migrated to a second processing engine included in the plurality of processing engines.

9 . A computer-implemented method, comprising:
managing access by one or more guest operating systems executing in a first computer system to a first processor in the first computer system, wherein the first processor is partitioned into a plurality of logical processors, wherein each logical processor in the plurality of logical processors:
performs functions of the first processor, while using a fraction of a total capacity of the first processor,
is assigned exclusive use of a subset of a plurality of hardware resources included in the first processor, and
executes in functional isolation from all other logical processors,
wherein a first interception layer:
routes a request generated via a first application programming interface (API) by a second processor in a second computer system to a first available hardware resource selected from the subset of the plurality of hardware resources, and
wherein a second interception layer included in the first computer system:
translates the request generated via the first API to API calls for a second API supported by a driver executing on the first processor in the first computer system,
subsequent to translating the request, transmits the request to the driver, and
routes a response to the request from the driver to the first interception layer executing on the second computer system.

10 . The computer-implemented method of claim 9 , wherein the first processor comprises a graphics processing unit (GPU).

11 . The computer-implemented method of claim 9 , wherein the first available hardware resource comprises a cache, a cluster of processing cores, a memory controller, a context switching unit, a scheduler, or a work distribution unit.

12 . The computer-implemented method of claim 9 , wherein a first logical processor in the plurality of logical processors is assigned exclusive use of a first percentage of the plurality of hardware resources and a second logical processor is assigned exclusive use of less than the first percentage of the plurality of hardware resources.

13 . The computer-implemented method of claim 9 , wherein each logical processor in the plurality of logical processors executes tasks associated with a different guest operating system included in the one or more guest operating systems.

14 . The computer-implemented method of claim 9 , wherein a first logical processor in the plurality of logical processors executes a first set of tasks in parallel with a second logical processor in the plurality of logical processors executing a second set of tasks.

15 . The computer-implemented method of claim 9 , wherein a first logical processor in the plurality of logical processors includes a plurality of processing engines, and wherein a first processing engine included in the plurality of processing engines executes a first set of processing tasks associated with a first processing context in a given time interval and a second processing engine included in the plurality of processing engines executes a second set of processing tasks associated with the first processing context in the given time interval.

16 . The computer-implemented method of claim 9 , wherein a first logical processor in the plurality of logical processors includes a plurality of processing engines, wherein a first processing context executing within a first processing engine included in the plurality of processing engines is migrated to a second processing engine included in the plurality of processing engines.

17 . A system, comprising:
a first interception layer executing on a first processor in a first computing system, wherein the first interception layer is configured to:
intercept a request generated via a first application programming interface (API) to a second processor included in a second computer system by a software application executing on the first computing system, wherein the second computing system includes the second processor rathe

Assignees

• Nvidia Corp

Inventors

• Duluk Jr Jerome F
• Palmer Gregory Scott
• Evans Jonathon Stuart Ramsay
• Singh Shailendra
• Duncan Samuel H
• Gandhi Wishwesh Anil
• Shah Lacky V
• Wen Sonata Gale
• Su Feiqi
• Deming James Leroy
• Menezes Alan
• Vaidya Pranav
• Joginipally Praveen
• Purcell Timothy John
• Mandal Manas

Classifications

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F9/45533

  Hypervisors; Virtual machine monitors · CPC title

• G06F9/4881

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F2209/509

  Offload · CPC title

• G06F9/5077

  Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title