Processing device, processing system, and processing method

Patent metadata

Field	Value
Publication number	US-12498753-B2
Application number	US-202418760422-A
Country	US
Kind code	B2
Filing date	Jul 1, 2024
Priority date	Jul 21, 2023
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

A processing device according to an aspect of the present disclosure includes: a toggle signal reception circuit configured to receive a toggle signal a value of which transitions between binary values at a timing of a pulse of a frequency-divided clock signal in which a periodic pattern signal is repeated, pulses of the periodic pattern signal being generated by masking predetermined pulses of a mask pulse number among consecutive pulses of a periodic pulse number in an input clock signal, the mask pulse number being smaller than the periodic pulse number; and a communication circuit configured to communicate with another processing device operated by the frequency-divided clock signal at the timing of the pulse of the frequency-divided clock signal among the pulses of the input clock signal, the timing of the pulse of the frequency-divided clock signal being specified using the toggle signal.

First claim

What is claimed is:

1 . A processing device comprising:
a toggle signal reception circuit configured to receive a toggle signal a value of which transitions between binary values at a timing of a pulse of a frequency-divided clock signal in which a periodic pattern signal is repeated, pulses of the periodic pattern signal being generated by masking predetermined pulses of a mask pulse number among consecutive pulses of a periodic pulse number in an input clock signal, the mask pulse number being smaller than the periodic pulse number; and a communication circuit configured to communicate with another processing device operated by the frequency-divided clock signal at the timing of the pulse of the frequency-divided clock signal among the pulses of the input clock signal, the timing of the pulse of the frequency-divided clock signal being specified using the toggle signal.

2 . The processing device according to claim 1 , wherein
the toggle signal includes a toggle signal marker that is a pattern of the signal, and the pattern of the signal of the toggle signal marker is present only in a portion in the toggle signal marker of the toggle signal.

3 . The processing device according to claim 2 , wherein
the toggle signal marker is a signal pattern generated in the toggle signal by a partial portion of a marker part that is a head portion of the periodic pattern signal, and the processing device further comprises: a detection circuit configured to detect the toggle signal marker from the toggle signal; and a specification circuit configured to specify the timing of the pulse of the frequency-divided clock signal from a timing of the detected toggle signal marker.

4 . The processing device according to claim 3 , wherein
the frequency-divided clock signal includes the marker part including at least one unmasked pulse in the head portion of the periodic pattern signal, and a pattern of pulses in the marker part appears only in a portion in the marker part of the frequency-divided clock signal.

5 . The processing device according to claim 3 , wherein
in a case where an output pulse number obtained by subtracting the mask pulse number from the periodic pulse number is a value obtained by subtracting one from the periodic pulse number, and in a case where the output pulse number is larger than or equal to two and the output pulse number is smaller than a value obtained by dividing the periodic pulse number by two, the marker part includes unmasked pulses at two consecutive output clock timings that are timings at which the pulses are output as the frequency-divided clock signal in a case where the pulses are not masked, and a non-marker part that is a part other than the marker part of the periodic pattern signal does not include the unmasked pulses at the two consecutive output clock timings, and in a case where the output pulse number is larger than or equal to the value obtained by dividing the periodic pulse number by two, and the output pulse number is smaller than the value obtained by subtracting one from the periodic pulse number, and in a case where the output pulse number is one, pulses are masked at two or more consecutive output clock timings in the marker part, and pulses are not masked at two consecutive output clock timings in the non-marker part.

6 . The processing device according to claim 2 , wherein
in a case where an output pulse number obtained by subtracting the mask pulse number from the periodic pulse number is a value obtained by subtracting one from the periodic pulse number, the toggle signal marker is a signal for a cycle where the value of the toggle signal does not transition, in a case where the output pulse number is larger than or equal to two and the output pulse number is smaller than a value obtained by dividing the periodic pulse number by two, the toggle signal marker is a signal for two consecutive cycles where the value of the toggle signal does not transition, in a case where the output pulse number is larger than or equal to the value obtained by dividing the periodic pulse number by two and the output pulse number is smaller than the value obtained by subtracting one from the periodic pulse number, the toggle signal marker is a signal for two consecutive cycles where the value of the toggle signal transitions, and in a case where the output pulse number is one, the toggle signal marker is a signal for a cycle where the value of the toggle signal transitions.

7 . A processing system including the processing device according to claim 1 , the processing system comprising:
a frequency-divided clock generation device that generates the frequency-divided clock signal from the input clock signal; and a toggle signal generation device that receives the frequency-divided clock signal and generates the toggle signal using the frequency-divided clock signal.

8 . The processing system according to claim 7 , wherein
the frequency-divided clock generation device is configured to: perform determination whether to mask each of the pulses of the input clock signal from the periodic pulse number and a non-mask pulse number that is the number of unmasked pulses; generate a mask signal indicating a result of the determination; and according to the mask signal, mask the pulse determined to be masked and directly output the pulse determined not to be masked.

9 . The processing system according to claim 8 , wherein
the frequency-divided clock generation device is further configured to: generate a marker part mask signal that is the mask signal for a marker part determined according to the periodic pulse number and the non-mask pulse number in the marker part, the marker part being a head portion of the periodic pattern signal; generate a non-marker part mask signal, the non-marker part mask signal being the mask signal for a non-marker part that is a part other than the marker part of the periodic pattern signal, in such a way that a pattern of unmasked pulses in the non-marker part is same as a pattern of unmasked pulses in the periodic clock signal in a case where rational number frequency division is performed according to a predetermined rational number frequency division algorithm at a frequency division ratio determined by a second periodic pulse number and a second non-mask pulse number, the second periodic pulse number being obtained by subtracting the number of pulses in the marker part from the periodic pulse number, the second non-mask pulse number being obtained by subtracting the number of unmasked pulses included in the marker part from the unmasked pulse number; and output the marker part mask signal as the mask signal while the marker part of the periodic pattern signal is output, and output the non-marker part mask signal as the mask signal while the non-marker part of the periodic pattern signal is output.

10 . A processing method comprising:
receiving a toggle signal a value of which transitions between binary values at a timing of a pulse of a frequency-divided clock signal in which a periodic pattern signal is repeated, pulses of the periodic pattern signal being generated by masking predetermined pulses of a mask pulse number among consecutive pulses of a periodic pulse number in an input clock signal, the mask pulse number being smaller than the periodic pulse number; and communicating with another processing device operated by the frequency-divided clock signal at the timing of the pulse of the frequency-divided clock signal among the pulses of the input clock signal, the timing of the pulse of the frequency-divided clock signal being specified using the toggle signal.

11 . The processing method according to cl

Assignees

• Nec Corp

Inventors

• Shibayama Atsufumi

Classifications

• H03K23/662

  by adding or suppressing pulses · CPC title

• G06F1/04

  Generating or distributing clock signals or signals derived directly therefrom · CPC title

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title