Display substrate, manufacturing method thereof and display device

US12498606B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12498606-B2
Application numberUS-202117908976-A
CountryUS
Kind codeB2
Filing dateOct 29, 2021
Priority dateOct 29, 2021
Publication dateDec 16, 2025
Grant dateDec 16, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes a display region, a peripheral region a plurality of signal lines configured to provide signals to the display region; a plurality of contact pads configured to be electrically connected with the plurality of signal lines; at least two conductive connection lines provided on a side of the plurality of contact pads facing away from the display region. The at least two conductive connection lines include a first conductive connection line closest to the plurality of contact pads in a first direction from the display region to the peripheral region. At least part of the plurality of contact pads are provided in a first conductive layer, the first conductive connection line is provided in a second conductive layer, and the first conductive layer and the second conductive layer are different layers.

First claim

Opening claim text (preview).

What is claimed is: 1 . A display substrate, comprising: a display region and a peripheral region provided on at least one side of the display region, the display substrate further comprising: a plurality of signal lines, provided in the display region and configured to provide signals to the display region; a plurality of contact pads, provided in the peripheral region and configured to be electrically connected with the plurality of signal lines; and at least two conductive connection lines, provided in the peripheral region and on a side of the plurality of contact pads facing away from the display region, wherein the at least two conductive connection lines are spaced from each other, and the at least two conductive connection lines comprise a first conductive connection line closest to the plurality of contact pads in a first direction from the display region to the peripheral region, wherein the plurality of contact pads comprise a first group of contact pads and a second group of contact pads, and the first group of contact pads are provided in a first conductive layer, wherein the first group of contact pads and the first conductive connection line are provided in different layers; the first group of contact pads and the second group of contact pads are staggered with each other in the first direction, and the second group of contact pads are further away from the first conductive connection line than the first group of contact pads. 2 . The display substrate according to claim 1 , wherein: the first group of contact pads and the second group of contact pads are staggered in the first direction by x contact pads, where 0.5≤x≤1.5; and the first group of contact pads and the second group of contact pads do not overlap with the at least two conductive connection lines in a direction perpendicular to the display substrate. 3 . The display substrate according to claim 1 , wherein: the peripheral region comprises a peripheral bonding region and a peripheral transition region provided between the peripheral bonding region and the display region; the display substrate further comprises a plurality of conductive transition lines provided in the peripheral transition region and connected with the plurality of signal lines; the plurality of contact pads are provided in the peripheral bonding region and connected with the plurality of conductive transition lines; the plurality of signal lines include a first group of signal lines and a second group of signal lines, the plurality of conductive transition lines comprise a first group of conductive transition lines and a second group of conductive transition lines, and the first group of conductive transition lines are connected to the first group of signal lines on a side close to the first group of signal lines and are connected to the first group of contact pads on a side close to the first group of contact pads; and the first group of signal lines, the first group of conductive transition lines and the first group of contact pads are all provided in the first conductive layer. 4 . The display substrate according to claim 3 , wherein: the second group of conductive transition lines are connected to the second group of signal lines on a side close to the second group of signal lines and are connected to the second group of contact pads on a side close to the second group of contact pads; the second group of signal lines is provided in the first conductive layer, and the second group of conductive transition lines and the second group of contact pads are provided in a second conductive layer. 5 . The display substrate according to claim 4 , further comprising: a base substrate; and a display pixel array provided on the base substrate, the display pixel array being provided in the display region, the display pixel array comprising a display pixel driving circuit, a first display electrode, a passivation layer and a second display electrode, and the first display electrode and the second display electrode being configured to generate an electric field, wherein: the display pixel driving circuit comprises a thin film transistor, the thin film transistor comprises a gate electrode, a source electrode, a drain electrode and an interlayer insulation layer, the interlayer insulation layer is provided between the gate electrode and the source electrode as well as the drain electrode in a direction perpendicular to the base substrate; the first display electrode is provided in a same layer as the source electrode as well as the drain electrode, and the first display electrode is electrically connected with one of the source electrode and the drain electrode; the passivation layer is provided on a side of the first display electrode facing away from the base substrate; the second display electrode is provided on a side of the passivation layer facing away from the first display electrode; and one of the first conductive layer and the second conductive layer is provided in a same layer as the gate electrode and the other of the first conductive layer and the second conductive layer is provided in a same layer as the source electrode as well as the drain electrode. 6 . The display substrate according to claim 5 , wherein: the source electrode and the drain electrode are provided on a side of the gate electrode facing away from the base substrate; the first conductive layer is provided on a side of the second conductive layer facing away from the base substrate; the first conductive layer, the source electrode and the drain electrode are provided in a same layer using a same material, and the second conductive layer and the gate electrode are provided in a same layer using a same material. 7 . The display substrate according to claim 5 , wherein: the passivation layer and the interlayer insulation layer are configured to extend to the peripheral region; the interlayer insulation layer is provided on a side of the second group of conductive transition lines facing away from the base substrate; the second group of signal lines is provided on a side of the interlayer insulation layer facing away from the second group of conductive transition lines; the passivation layer is provided on a side of the second group of signal lines and the interlayer insulation layer facing away from the base substrate; the peripheral transition region is further provided with a first via hole, a second via hole and a transition conductive pattern, the first via hole penetrates the passivation layer to expose at least one signal line in the second group of signal lines, the second via hole penetrates the passivation layer and the interlayer insulation layer to expose at least one conductive transition line, corresponding to the at least one signal line, in the second group of conductive transition lines, the transition conductive pattern covers the first via hole and the second via hole to electrically connect the at least one signal line and the at least one conductive transition line. 8 . The display substrate according to claim 1 , wherein the at least two conductive connection lines further comprise: a second conductive connection line, provided on a side of the first conductive connection line facing away from the plurality of contact pads. 9 . The display substrate according to claim 8 , wherein the first conductive connection line and the second conductive connection line are configured to transmit signals provided by an external circuit. 10 . The display substrate according to claim 1 , further comprising: a base substrate; a display pixel array provided on the base substrate, the display pixel array being provided in the display region;

Assignees

Inventors

Classifications

  • of multiple TFTs · CPC title

  • adapted for preventing breakage, peeling or short circuiting · CPC title

  • wherein the TFTs are in active matrices · CPC title

  • Wiring, e.g. gate line, drain line · CPC title

  • characterised by their geometrical arrangement · CPC title

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What does patent US12498606B2 cover?
A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes a display region, a peripheral region a plurality of signal lines configured to provide signals to the display region; a plurality of contact pads configured to be electrically connected with the plurality of signal lines; at least two conductive connection lines provided on a s…
Who is the assignee on this patent?
Chongqing Boe Optoelectronics Tech Co Ltd, Boe Technology Group Co Ltd, Beijing Boe Technology Dev Co Ltd
What technology area does this patent fall under?
Primary CPC classification G02F1/134309. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 16 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).