LED display unit group and display panel

US12495651B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12495651-B2
Application numberUS-202117910295-A
CountryUS
Kind codeB2
Filing dateMar 25, 2021
Priority dateMar 31, 2020
Publication dateDec 9, 2025
Grant dateDec 9, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided are a LED display unit group and a display panel. The LED display unit group includes a circuit board and pixel units. The circuit board includes N metal wiring layers stacked in sequence and an insulating plate disposed between adjacent metal wiring layers, and the N metal wiring layers are electrically connected through conductive vias on the insulating plate. The pixel units are arranged in an array of m rows and n columns and disposed on the circuit board. Each pixel unit includes at least two LED light-emitting chips with different emitted colors, each LED light-emitting chip is fixed on a first metal wiring layer. The first metal wiring layer includes m common A-electrode pads, A-electrode pads, and B-electrode pads. All the A-electrode pads corresponding to each row of pixel units are integrally formed with and electrically connected to one corresponding common A-electrode pad.

First claim

Opening claim text (preview).

What is claimed is: 1 . A light-emitting diode (LED) display unit group, comprising: a circuit board comprising N metal wiring layers stacked in sequence and at least one insulating plate, wherein each of the at least one insulating plate is disposed between adjacent metal wiring layers among the N metal wiring layers, the N metal wiring layers are electrically connected through conductive vias on the at least one insulating plate, and N≥2; and pixel units arranged in an array of m rows and n columns and disposed on the circuit board, wherein each of the pixel units comprises at least two LED light-emitting chips with different emitted colors, each of the at least two LED light-emitting chips is fixed on a first metal wiring layer among the N metal wiring layers, m≥2, and n≥2; wherein the first metal wiring layer comprises m common A-electrode pads, a plurality of A-electrode pads, and a plurality of B-electrode pads, wherein the plurality of A-electrode pads are disposed in one-to-one correspondence with A electrodes of LED light-emitting chips, the plurality of B-electrode pads are disposed in one-to-one correspondence with B electrodes of the LED light-emitting chips, and all A-electrode pads corresponding to each row of pixel units in the pixel units are integrally formed with and electrically connected to one of the m common A-electrode pads corresponding to the each row of pixel units; and each of the m common A-electrode pads comprises at least one bend part, and a bending direction of the at least one bend part of one of the m common A-electrode pads corresponding to a first row of pixel units in the pixel units is opposite to a bending direction of the at least one bend part of one of the m common A-electrode pads corresponding to an m-th row of pixel units in the pixel units; wherein in two adjacent pixel units of the pixel units in a same row, a direction of a connection line from an A electrode to a B electrode of one of the at least two LED light-emitting chips in one of the two adjacent pixel units is opposite to a direction of a connection line from an A electrode to a B electrode of one of the at least two LED light-emitting chips in another one of the two adjacent pixel units. 2 . The LED display unit group of claim 1 , wherein an N-th metal wiring layer among the N metal wiring layers comprises m common A-electrode pins and 3n common B-electrode pins, wherein one of the m common A-electrode pins is electrically connected to one of the m common A-electrode pads corresponding to A electrodes of all LED light-emitting chips in one row of pixel units in the pixel units, and one of the 3n common B-electrode pins is electrically connected to a plurality of B-electrode pads corresponding to B electrodes of all LED light-emitting chips with a same emitted color in one column of pixel units in the pixel units. 3 . The LED display unit group of claim 1 , wherein a plurality of A-electrode pads of one of the pixel units in an i-th column and a row, a plurality of A-electrode pads of one of the pixel units in an (i+1)-th column and the same row, and one of the m common A-electrode pads connected to the plurality of A-electrode pads of the one of the pixel units in the i-th column and the row and the plurality of A-electrode pads of the one of the pixel units in the (i+1)-th column and the same row are U-shaped, wherein i<n. 4 . The LED display unit group of claim 3 , wherein a plurality of B-electrode pads of the one of the pixel units in the i-th column and the row and a plurality of B-electrode pads of the one of the pixel units in the (i+1)-th column and the same row are disposed in a U-shaped opening, wherein i is an odd number. 5 . The LED display unit group of claim 1 , wherein conductive vias electrically connected to a plurality of B-electrode pads corresponding to all the at least two LED light-emitting chips of each of the pixel units are not on a same vertical line. 6 . The LED display unit group of claim 1 , wherein each of the pixel units comprises following three LED light-emitting chips: a LED light-emitting chip with a first emitted color, a LED light-emitting chip with a second emitted color, and a LED light-emitting chip with a third emitted color, wherein the three LED light-emitting chips with different emitted colors are in one-to-one correspondence with three B-electrode pads of the plurality of B-electrode pads, and the three B-electrode pads in one-to-one correspondence with the three LED light-emitting chips with different emitted colors are a first B-electrode pad corresponding to the LED light-emitting chip with the first emitted color, a second B-electrode pad corresponding to the LED light-emitting chip with the second emitted color, and a third B-electrode pad corresponding to the LED light-emitting chip with the third emitted color, respectively. 7 . The LED display unit group of claim 6 , wherein in a case where N=4, a metal wire connecting all first B-electrode pads of each column of pixel units in the pixel units and a metal wire connecting all third B-electrode pads of each column of pixel units in the pixel units are disposed on a third metal wiring layer among the N metal wiring layers. 8 . The LED display unit group of claim 6 , wherein in a case where N=4, a metal wire connecting all second B-electrode pads of each column of pixel units in the pixel units is disposed on a second metal wiring layer among the N metal wiring layers. 9 . The LED display unit group of claim 1 , wherein an identification mark for identifying electrodes of pins is disposed on one of the at least one insulating plate in contact with an N-th metal wiring layer among the N metal wiring layers. 10 . The LED display unit group of claim 2 , wherein an identification mark that is used for identifying electrodes of pins and is made of a same material as the m common A-electrode pins and the 3 n common B-electrode pins is disposed on one of the at least one insulating plate in contact with an N-th metal wiring layer among the N metal wiring layers, and the identification mark is not electrically connected. 11 . The LED display unit group of claim 10 , wherein a distance between every two adjacent ones of the identification mark, the m common A-electrode pins, and the 3 n common B-electrode pins is the same. 12 . A display panel, comprising a light-emitting diode (LED) display unit group, wherein the LED display unit group comprises: a circuit board comprising N metal wiring layers stacked in sequence and at least one insulating plate, wherein each of the at least one insulating plate is disposed between adjacent metal wiring layers among the N metal wiring layers, the N metal wiring layers are electrically connected through conductive vias on the at least one insulating plate, and N≥2; and pixel units arranged in an array of m rows and n columns and disposed on the circuit board, wherein each of the pixel units comprises at least two LED light-emitting chips with different emitted colors, each of the at least two LED light-emitting chips is fixed on a first metal wiring layer among the N metal wiring layers, m≥2, and n≥2; wherein the first metal wiring layer comprises m common A-electrode pads, a plurality of A-electrode pads, and a plurality of B-electrode pads, wherein the plurality of A-electrode pads are disposed in one-to-one correspondence with A electrodes of LED light-emitting chips, the plurality of B-electrode pads are disposed in one-to-one correspondence with B electrodes of the LED light-emitting chips, and all A-electrode pads corresponding to each row of pixel units in the pixel units are integrally formed with and electrically connected to

Assignees

Inventors

Classifications

  • H10W90/00Primary

    Package configurations · CPC title

  • Two-dimensional arrangements, e.g. asymmetric LED layout · CPC title

  • characterised by their shape · CPC title

  • H10H20/857Primary

    Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

  • of interconnections · CPC title

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What does patent US12495651B2 cover?
Provided are a LED display unit group and a display panel. The LED display unit group includes a circuit board and pixel units. The circuit board includes N metal wiring layers stacked in sequence and an insulating plate disposed between adjacent metal wiring layers, and the N metal wiring layers are electrically connected through conductive vias on the insulating plate. The pixel units are arr…
Who is the assignee on this patent?
Foshan Nationstar Optoelectronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 09 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).