Semiconductor package including stack structure of logic chip and sensing chips

Patent metadata

Field	Value
Publication number	US-12495633-B2
Application number	US-202217745010-A
Country	US
Kind code	B2
Filing date	May 16, 2022
Priority date	May 17, 2021
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

A semiconductor package including a substrate including a through hole, an image sensor structure on the substrate, and a first transparent substrate on the substrate and spaced apart from the image sensor structure may be provided. The image sensor structure includes a logic chip on the substrate, a first sensing chip on an active surface of the logic chip, and a second sensing chip on an inactive surface of the logic chip and connected to the active surface of the logic chip through a first via that vertically penetrates the logic chip. On a bottom surface of the logic chip, at least a portion of one of the first sensing chip and the second sensing chip is in the through hole.

First claim

What is claimed is:

1 . A semiconductor package, comprising:
a substrate including a through hole; an image sensor structure on the substrate; and a first transparent substrate on the substrate and spaced apart from the image sensor structure, the image sensor structure being vertically between the first transparent substrate and the substrate, wherein the image sensor structure includes,
a logic chip on the substrate,
a first sensing chip on a first surface of the logic chip, the first surface including an integrated circuit thereon, and
a second sensing chip on a second surface of the logic chip, the second surface of the logic chip being opposite to the first surface of the logic chip, the second sensing chip connected to the first surface of the logic chip through a first via that vertically penetrates the logic chip,
wherein, on the second surface of the logic chip, one of the first sensing chip or the second sensing chip is in the through hole, wherein the logic chip is directly connected to the substrate through a connection terminal, and wherein the first surface of the logic chip faces the substrate, and the first sensing chip is in the through hole of the substrate.

2 . The semiconductor package of claim 1 , wherein
the connection terminal is on the second surface of the logic chip, and the logic chip is mounted on the substrate through the connection terminal.

3 . The semiconductor package of claim 2 , wherein
the connection terminal is between the substrate and the logic chip, and when viewed in a plan view, the logic chip is outside the through hole.

4 . The semiconductor package of claim 1 , wherein
the first sensing chip and the logic chip are bonded each other in direct bonding manner, a dielectric pattern of the first sensing chip and a dielectric pattern of the logic chip are in contact with each other to constitute a single body, or a pad of the first sensing chip and a pad of the logic chip are in contact with each other to constitute a single body.

5 . The semiconductor package of claim 1 , wherein the first sensing chip and the logic chip are connected to each other through a connection terminal between the first sensing chip and the logic chip.

6 . The semiconductor package of claim 1 , wherein
the substrate has a recess region that extends into the substrate from a bottom surface of the substrate, a width of the recess region being greater than a width of the through hole, the through hole of the substrate penetrates a central portion of the recess region, and a second transparent substrate is provided in the recess region.

7 . The semiconductor package of claim 1 , wherein the first transparent substrate is spaced apart from the image sensor structure by a spacer between the first transparent substrate and the substrate.

8 . The semiconductor package of claim 1 , wherein
the image sensor structure further includes a memory chip between the logic chip and the second sensing chip, the first via penetrates the memory chip and the logic chip from the second sensing chip and connected to the first surface of the logic chip, and the first sensing chip is connected to the memory chip through a second via that vertically penetrates the first sensing chip and the logic chip.

9 . The semiconductor package of claim 1 , wherein
the image sensor structure further includes a memory chip between the logic chip and the first sensing chip, and the second sensing chip is connected to the memory chip through a second via that vertically penetrates the second sensing chip and the logic chip.

10 . A semiconductor package, comprising:
a substrate having a through hole and a recess region, the through hole penetrating the substrate, the recess region being on a lower portion of the substrate; a logic chip on the substrate and covering the through hole; a first sensing chip on the logic chip; a second sensing chip below the logic chip and being entirely within the through hole, when viewed in a plan view; a first transparent substrate on the substrate; a spacer between the substrate and the first transparent substrate, the spacer separating the first transparent substrate and the first sensing chip from each other; and a second transparent substrate in the recess region of the substrate, wherein one of the first sensing chip or the second sensing chip is connected to a first surface of the logic chip through a first via that vertically penetrates the logic chip, the first surface including an integrated circuit thereon, wherein the second sensing chip has a width less than a width of the logic chip, the second sensing chip is entirely within the through hole when viewed in a plan view, and wherein the other of the first sensing chip and the second sensing chip is on the first surface of the logic chip.

11 . The semiconductor package of claim 10 , wherein
the first surface of the logic chip faces the first transparent substrate, and the second sensing chip is connected to the first surface of the logic chip by the first via.

12 . The semiconductor package of claim 10 , wherein
the first surface of the logic chip faces the second transparent substrate, and the first sensing chip is connected to the first surface of the logic chip by the first via.

13 . The semiconductor package of claim 10 , wherein
a connection terminal is between the substrate and the logic chip and outside the through hole, and the logic chip is mounted on the substrate through the connection terminal.

14 . The semiconductor package of claim 10 , wherein
the logic chip is attached to the substrate through an adhesion layer, and the logic chip is mounted on the substrate through a connection wire that connects a top surface of the logic chip to a top surface of the substrate.

15 . A semiconductor package, comprising:
a substrate including a through hole; a chip stack on the substrate; and a first transparent substrate on the chip stack, wherein the chip stack includes, a first semiconductor chip on a top surface of the substrate; a second semiconductor chip on the first semiconductor chip, the second semiconductor chip on a first surface of the first semiconductor chip, the first surface including an integrated circuit thereon; and a third semiconductor chip on a second surface of the first semiconductor chip, the second surface of the first semiconductor chip being opposite to the first surface of the first semiconductor chip, the third semiconductor chip penetrating a central portion of the substrate and being exposed by a bottom surface of the substrate, wherein a first pad of the first semiconductor chip is in direct contact with a second pad of the second semiconductor chip, wherein the third semiconductor chip is coupled to the first surface of the first semiconductor chip through a first via that vertically penetrates the first semiconductor chip, wherein the first semiconductor chip includes a logic chip, and wherein the second semiconductor chip includes an image sensing chip, wherein the third semiconductor chip is entirely within the through hole on the second surface of the first semiconductor chip, when viewed in a plan view, wherein the third semiconductor chip has a width less than a width of the first semiconductor chip, and wherein the logic chip is directly connected to the substrate through a connection terminal.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Kyungkyu
• Lee Dong-Hun
• Kim Woonbae
• Lee Daeho
• Lee Jungpil

Classifications

• H10F39/8053 Primary

  Colour filters · CPC title

• H10F39/811

  Interconnections · CPC title

• H10F39/182

  Colour image sensors · CPC title

• H10F39/809 Primary

  of hybrid image sensors · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title