Semiconductor device and forming method thereof

Patent metadata

Field	Value
Publication number	US-12495548-B2
Application number	US-202318350259-A
Country	US
Kind code	B2
Filing date	Jul 11, 2023
Priority date	Mar 29, 2023
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate, a first source/drain region and a second source/drain region disposed within the substrate, and a gate structure disposed on the substrate and between the first source/drain region and the second source/drain region. The semiconductor device further includes an interlayer dielectric layer disposed over the first source/drain region, the second source/drain region, and the gate structure. The interlayer dielectric layer includes a second trench extending into the second source/drain region. The semiconductor device further includes a dielectric layer disposed in the second trench, and a second source/drain contact disposed over the second source/drain region and filling the remaining portion of the second trench.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate; a first source/drain region and a second source/drain region, disposed within the substrate; a gate structure, disposed on the substrate and between the first source/drain region and the second source/drain region; an interlayer dielectric layer, disposed over the first source/drain region, the second source/drain region, and the gate structure, wherein the interlayer dielectric layer comprises a second trench extending into the second source/drain region; a dielectric layer, disposed in the second trench; and a second source/drain contact, disposed over the second source/drain region and filling a remaining portion of the second trench.

2 . The semiconductor device as claimed in claim 1 , wherein the dielectric layer is between the second source/drain region and the second source/drain contact, covers a bottom of the second trench, and is arc-shaped, wherein a central portion of the dielectric layer is lower than an upper surface of the second source/drain region, and wherein an edge portion of the dielectric layer is level with or lower than the upper surface of the second source/drain region but is higher than the central portion.

3 . The semiconductor device as claimed in claim 1 , wherein the dielectric layer covers a bottom and a sidewall of the second trench, such that the dielectric layer is U-shaped and wraps around the second source/drain contact, wherein the dielectric layer at a bottom portion of the source/drain contact is lower than an upper surface of the second source/drain region.

4 . The semiconductor device as claimed in claim 1 , further comprising a second conductive line, wherein the second conductive line is disposed over and in contact with the second source/drain contact.

5 . The semiconductor device as claimed in claim 4 , wherein the second conductive line is a source line.

6 . The semiconductor device as claimed in claim 1 , wherein the interlayer dielectric layer further comprises a first trench extending into the first source/drain region, and a silicide layer disposed in the bottom of the first trench.

7 . The semiconductor device as claimed in claim 6 , further comprising a first source/drain contact disposed over the first source/drain region and filling a remaining portion of the first trench, such that the silicide layer is between the first source/drain region and the first source/drain contact.

8 . The semiconductor device as claimed in claim 6 , further comprising a first conductive line, wherein the first conductive line is disposed over and in contact with the first source/drain contact.

9 . The semiconductor device as claimed in claim 8 , wherein the first conductive line is a bit line.

10 . The semiconductor device as claimed in claim 1 , wherein the second source/drain contact comprises a lower portion in contact with the second source/drain region and an upper portion disposed on the lower portion, and wherein the dielectric layer is disposed between the lower portion and the upper portion.

11 . The semiconductor device as claimed in claim 10 , wherein the dielectric layer is plate-shaped.

12 . The semiconductor device as claimed in claim 10 , wherein the dielectric layer is U-shaped, and wherein the dielectric layer wraps around the upper portion of the second source/drain contact, such that a width of the upper portion is less than a width of the lower portion.

13 . The semiconductor device as claimed in claim 10 , wherein the lower portion of the second source/drain contact includes polysilicon.

14 . A method for forming a semiconductor device, comprising:
providing a substrate; forming a gate structure on the substrate; forming a first source/drain region and a second source/drain region in the substrate, wherein the first source/drain region and the second source/drain region are located on opposite sides of the gate structure; forming an interlayer dielectric layer on the gate structure, the first source/drain region, and the second source/drain region; etching the interlayer dielectric layer and the second source/drain region to form a second source/drain trench, wherein the second source/drain trench comprises a second recess within the second source/drain region; forming a dielectric layer in the second source/drain trench; and forming a second source/drain contact in the second source/drain trench.

15 . The method as claimed in claim 14 , wherein the forming the dielectric layer comprises forming the dielectric layer within the second recess, wherein the dielectric layer is arc-shaped and a central portion of the dielectric layer is lower than an upper surface of the second source/drain region, and wherein an edge portion of the dielectric layer is level with or lower than the upper surface of the second source/drain region but is higher than the central portion.

16 . The method as claimed in claim 14 , wherein the forming of the dielectric layer comprises forming the dielectric layer within the second source/drain trench, wherein the dielectric layer is U-shaped and in contact with a bottom of the second recess and a sidewall of the second source/drain trench.

17 . The method as claimed in claim 14 , further comprising:
forming a polysilicon layer within the second source/drain trench before forming the dielectric layer; forming the dielectric layer on the polysilicon layer; and forming a conductive material on the dielectric layer.

18 . The method as claimed in claim 14 , further comprising:
forming a polysilicon layer within the second source/drain trench before forming the dielectric layer; forming the dielectric layer on the polysilicon layer and on a sidewall of a remaining portion of the second source/drain trench, wherein the dielectric layer is U-shaped; and forming a conductive material on the dielectric layer.

19 . The method as claimed in claim 14 , further comprising: etching the interlayer dielectric layer and the first source/drain region to form a first source/drain trench, wherein the first source/drain trench comprises a first recess within the first source/drain region; forming a silicide layer in the first recess; and forming a first source/drain contact in the first source/drain trench.

20 . The method as claimed in claim 19 , further comprising:
forming a first conductive line on the first source/drain contact, wherein the first conductive line is in contact with the first source/drain contact and is a bit line; and forming a second conductive line on the second source/drain contact, wherein the second conductive line is in contact with the second source/drain contact and is a source line.

Assignees

• Winbond Electronics Corp
• Windbond Electronics Corp

Inventors

• Wei Hung-Yu

Classifications

• H10B20/25 Primary

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