Delta-sigma modulator with anti-windup circuit

Patent metadata

Field	Value
Publication number	US-12494798-B2
Application number	US-202318127848-A
Country	US
Kind code	B2
Filing date	Mar 29, 2023
Priority date	Mar 29, 2023
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

A delta-sigma modulator includes a loop filter circuit having a first input that receives an input signal and a second input that receives a feedback signal. The loop filter circuit generates a filtered signal. A quantizer circuit quantizes the integrated signal to generate an output signal. An anti-windup circuit detects instances where the integrated signal is outside an input signal input of the quantizer circuit and in response thereto generates a dead zone signal having a magnitude and sign corresponding to a difference between the filtered signal and the input signal range. The feedback signal is a sum of the output signal and the dead zone signal.

First claim

What is claimed is:

1 . A delta-sigma modulator, comprising:
a loop filter circuit having a first input configured to receive an input signal, a second input configured to receive a feedback signal, and an output configured to generate a filtered signal; a clamping circuit having an input configured to receive the filtered signal and an output configured to generate a clamped filtered signal; a quantizer circuit configured to receive the clamped filtered signal and generate a quantizer output signal; a first summation circuit configured to generate a dead zone signal from a difference between the filtered signal and the clamped filtered signal; and a second summation circuit configured to generate the feedback signal from a sum of the quantizer output signal and the dead zone signal.

2 . The delta-sigma modulator of claim 1 , wherein the loop filter circuit comprises a cascade of integrators and a summation circuit for each integrator, the summation circuit including a first input configured to receive the input signal, a second input configured to receive the feedback signal, and an output coupled to an input of the integrator.

3 . The delta-sigma modulator of claim 2 , wherein the cascade of integrators includes one or more of feed forward circuitry and feed back circuitry.

4 . The delta-sigma modulator of claim 1 , wherein the quantizer circuit comprises:
an analog-to-digital converter configured to receive the clamped filtered signal and generate an intermediate signal; and a digital-to-analog converter configured to convert the intermediate signal to generate the quantizer output signal.

5 . The delta-sigma modulator of claim 1 , wherein the quantizer circuit comprises a digital pulse width modulation (PWM) quantizer.

6 . The delta-sigma modulator of claim 1 , wherein the clamping circuit has maximum positive/negative clamp limits less than or equal to positive/negative limits of an input signal range of the quantizer circuit.

7 . A delta-sigma modulator, comprising:
a loop filter circuit having a first input configured to receive an input signal, a second input configured to receive a feedback signal, and an output configured to generate a filtered signal; a clamping circuit having an input configured to receive the filtered signal and an output configured to generate a clamped filtered signal; a quantizer circuit configured to receive the filtered signal and generate a quantizer output signal; a first summation circuit configured to generate a dead zone signal from a difference between the filtered signal and the clamped filtered signal; and a second summation circuit configured to generate the feedback signal from a sum of the quantizer output signal and the dead zone signal.

8 . The delta-sigma modulator of claim 7 , wherein the loop filter circuit comprises a cascade of integrators and a summation circuit for each integrator, the summation circuit including a first input configured to receive the input signal, a second input configured to receive the feedback signal, and an output coupled to an input of the integrator.

9 . The delta-sigma modulator of claim 8 , wherein the cascade of integrators includes one or more of feed forward circuitry and feed back circuitry.

10 . The delta-sigma modulator of claim 7 , wherein the quantizer circuit comprises:
an analog-to-digital converter configured to receive the clamped filtered signal and generate an intermediate signal; and a digital-to-analog converter configured to convert the intermediate signal to generate the quantizer output signal.

11 . The delta-sigma modulator of claim 7 , wherein the quantizer circuit comprises a digital pulse width modulation (PWM) quantizer.

12 . The delta-sigma modulator of claim 7 , wherein the clamping circuit has maximum positive/negative clamp limits less than or equal to positive/negative limits of an input signal range of the quantizer circuit.

13 . A delta-sigma modulator, comprising:
a loop filter circuit having a first input configured to receive an input signal, a second input configured to receive a feedback signal, and an output configured to generate a filtered signal; a quantizer circuit coupled to the output of the loop filter circuit and configured to generate a quantizer output signal; an anti-windup circuit configured to detect that the filtered signal is outside an input signal range of the quantizer circuit and generate a dead zone signal having a magnitude and sign corresponding to a difference between the filtered signal and the input signal range; and a summation circuit having a first input configured to receive the quantizer output signal, a second input configured to receive the dead zone signal, and an output configured to generate the feedback signal; wherein the anti-windup circuit comprises:
a clamping circuit having maximum positive/negative clamp limits less than or equal to positive/negative limits of the input signal range of the quantizer circuit, said anti-windup circuit having an input configured to receive the filtered signal and an output configured to generate a clamped filtered signal for application to an input of the quantizer circuit; and
a further summation circuit configured to generate the dead-zone signal from a difference between the filtered signal and the clamped filtered signal.

14 . The delta-sigma modulator of claim 13 , wherein the loop filter circuit comprises a cascade of integrators and a summation circuit for each integrator, the summation circuit including an input configured to receive the input signal, a further input configured to receive the feedback signal, and an output coupled to an input of the integrator, said cascade of integrators including one or more of feed forward circuitry and feed back circuitry.

15 . The delta-sigma modulator of claim 13 , wherein the quantizer circuit comprises a digital pulse width modulation (PWM) quantizer.

16 . A delta-sigma modulator, comprising:
a loop filter circuit having a first input configured to receive an input signal, a second input configured to receive a feedback signal, and an output configured to generate a filtered signal; a quantizer circuit coupled to the output of the loop filter circuit and configured to generate a quantizer output signal; an anti-windup circuit configured to detect that the filtered signal is outside an input signal range of the quantizer circuit and generate a dead zone signal having a magnitude and sign corresponding to a difference between the filtered signal and the input signal range; and a summation circuit having a first input configured to receive the quantizer output signal, a second input configured to receive the dead zone signal, and an output configured to generate the feedback signal; wherein the filtered signal is received at the input of the quantizer circuit and wherein the anti-windup circuit comprises:
a clamping circuit having maximum positive/negative clamp limits less than or equal to positive/negative limits of the input signal range of the quantizer circuit, said anti-windup circuit having an input configured to receive the filtered signal and an output configured to generate a clamped filtered signal; and
a further summation circuit configured to generate the dead-zone signal from a difference between the filtered signal and the clamped filtered signal.

17 . The delta-sigma modulator of claim 16 , wherein the quantizer circuit comprises:
an analog-to-digital converter configured to receive the clamped filtered signal and generate an intermediate signal; and a digita

Assignees

• St Microelectronics Int Nv
• Universita′ Pavia
• Torino Politecnico
• Univ Pavia

Inventors

• Stilgenbauer Francesco
• Botti Edoardo
• Malcovati Piero
• Crovetti Paolo Stefano
• Bonizzoni Edoardo
• De Ferrari Matteo

Classifications

• H03M3/436

  characterised by the order of the loop filter, e.g. error feedback type · CPC title

• H03M7/3035

  with provisions for rendering the modulator inherently stable, e.g. by restricting the swing within the loop, by removing part of the zeroes using local feedback loops, by positioning zeroes outside the unit circle causing the modulator to operate in a chaotic regime · CPC title

• H03M3/424

  the quantiser being a multiple bit one · CPC title

• H03M3/432

  the quantiser being a pulse width modulation type analogue/digital converter, i.e. differential pulse width modulation · CPC title

• H03K7/08

  Duration or width modulation {; Duty cycle modulation} · CPC title