Non-volatile memory device and corresponding method of operation

Patent metadata

Field	Value
Publication number	US-12494249-B2
Application number	US-202318464093-A
Country	US
Kind code	B2
Filing date	Sep 8, 2023
Priority date	Sep 14, 2022
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

In a non-volatile memory device, a memory sector is provided. The memory sector includes a plurality of tiles arranged horizontally. Each tile includes a plurality of memory cells arranged in horizontal word lines and vertical bit lines. A pre-decoder is configured to receive a set of encoded address signals to produce pre-decoding signals. A central row decoder is arranged in line with the plurality of tiles, receives the pre-decoding signals and produces level-shifted pull-up and pull-down driving signals for driving the word lines. First buffer circuits are arranged on a first side of each tile. Each of the first buffer circuits is coupled to a respective word line, receives a level-shifted pull-up driving signal and a level-shifted pull-down driving signal, and selectively pulls up or pulls down the respective word line as a function of the values of the received signals.

First claim

The invention claimed is:

1 . A non-volatile memory device, comprising:
at least one memory sector, wherein each memory sector includes a plurality of tiles arranged horizontally, wherein each tile of the plurality of tiles includes a plurality of memory cells arranged in an array of word lines extending horizontally and bit lines extending vertically, wherein the memory cells of a same row are coupled to a same word line and the memory cells of a same column are coupled to a same bit line; a pre-decoder configured to receive a set of encoded address signals and including a combinatorial circuit configured to produce pre-decoding signals as a function of said encoded address signals, wherein a combination of values of said pre-decoding signals identifies one word line within said at least one memory sector; a central row decoder arranged in line with said plurality of tiles of said at least one memory sector, wherein the central row decoder is configured to receive said pre-decoding signals, and process said pre-decoding signals to produce level-shifted pull-up driving signals and level-shifted pull-down driving signals for driving said word lines to a selected state or an unselected state; a respective first set of first buffer circuits arranged on a first side of each of said tiles of the plurality of tiles, wherein each of said first buffer circuits is coupled to a respective word line of the tile and is configured to:
receive a level-shifted pull-up driving signal out of said level-shifted pull-up driving signals and receive a level-shifted pull-down driving signal out of said level-shifted pull-down driving signals; and
selectively pull-up or pull-down said respective word line as a function of the values of said received level-shifted pull-up driving signal and level-shifted pull-down driving signal;
a respective second set of second buffer circuits arranged on a second side of each of said tiles of the plurality of tiles, wherein each of said second buffer circuits is coupled to a respective word line of the tile and is configured to:
receive a level-shifted pull-down driving signal out of said level-shifted pull-down driving signals; and
selectively pull-down said respective word line as a function of the value of said received level-shifted pull-down driving signal;
wherein:
said pre-decoding signals are in the voltage range of 0 V to about 0.9 V, and said level-shifted pull-up driving signals and level-shifted pull-down driving signals are in the voltage range of 0 V to a tile supply voltage of said at least one memory sector;
said central row decoder includes a plurality of pull-up driver circuits;
each of said pull-up driver circuits is configured to receive a respective first pre-decoding signal, a respective second pre-decoding signal and a respective third pre-decoding signal;
each of said pull-up driver circuits includes a level-shifting NAND logic gate configured to receive as input said respective first, second and third pre-decoding signals to assert and de-assert a respective pull-up control signal; and
each of said pull-up driver circuits is configured to produce a respective level-shifted pull-up driving signal by passing to its output a pull-up bias voltage in response to said respective pull-up control signal being de-asserted, and a shifted ground voltage in response to said respective pull-up control signal being asserted.

2 . The non-volatile memory device of claim 1 , wherein:
each of said first buffer circuits includes a pull-up p-channel MOS transistor and a p-channel cascode transistor having their current paths arranged in series between a tile supply voltage node that provides said tile supply voltage and the respective word line of the first buffer circuit, wherein a gate terminal of said pull-up p-channel MOS transistor receives said level-shifted pull-up driving signal and a gate terminal of said p-channel cascode transistor receives a pull-up cascode control signal; each of said first buffer circuits includes a pull-down n-channel MOS transistor and an n-channel cascode transistor having their current paths arranged in series between the respective word line of the first buffer circuit and a ground voltage node that provides a ground voltage, wherein a gate terminal of said pull-down n-channel MOS transistor receives said level-shifted pull-down driving signal and a gate terminal of said n-channel cascode transistor receives a pull-down cascode control signal; each of said second buffer circuits includes a further pull-down n-channel MOS transistor and a further n-channel cascode transistor having their current paths arranged in series between the respective word line of the second buffer circuit and said ground voltage node, wherein a gate terminal of said further pull-down n-channel MOS transistor receives said level-shifted pull-down driving signal and a gate terminal of said further n-channel cascode transistor receives said pull-down cascode control signal.

3 . The non-volatile memory device of claim 2 , wherein:
said tile supply voltage, said pull-up cascode control signal and said pull-down cascode control signal are routed vertically within said at least one memory sector; said level-shifted pull-down driving signals are routed horizontally within said at least one memory sector towards said first buffer circuits and said second buffer circuits that drive a same word line; and said level-shifted pull-up driving signals are routed both vertically and horizontally within said at least one memory sector towards groups of said first buffer circuits that drive groups of word lines.

4 . The non-volatile memory device of claim 1 , wherein:
said first buffer circuits in said first set of first buffer circuits are arranged in at least a first subset and a second subset, the first and second subset being spatially contiguous in the vertical direction; the first buffer circuits in the first subset receive a same level-shifted pull-up driving signal and are configured to drive a respective first subset of word lines of the tile; the first buffer circuits in the second subset receive a same level-shifted pull-up driving signal different from the level-shifted pull-up driving signal received by the first buffer circuits in the first subset, and are configured to drive a respective second subset of word lines of the tile; wherein the word lines of said first subset are interleaved with the word lines of said second subset.

5 . The non-volatile memory device of claim 1 , wherein:
said central row decoder includes a plurality of pull-down driver circuits; each of said pull-up driver circuits is configured to receive a respective first pre-decoding signal, a respective second pre-decoding signal and a respective third pre-decoding signal; each of said pull-up driver circuits includes a level-shifting NAND logic gate configured to receive as input said respective first, second and third pre-decoding signals to assert and de-assert a respective pull-down control signal; each of said pull-up driver circuits includes a plurality of buffer arrangements, wherein each of said buffer arrangements is configured to receive as input said respective pull-down control signal, a respective fourth pre-decoding signal and the complement of said fourth pre-decoding signal, and wherein each of said buffer arrangements is configured to produce a respective level-shifted pull-down driving signal by passing to its output said respective fourth pre-decoding signal in response to said respective pull-down control signal being de-asserted, and said ground voltage in response to said respective pull-down control signal being asserted or said complement of said fourth pre-decoding signal being asserted.

6 . A method of operating a non-volatile memory devi

Assignees

• St Microelectronics Srl
• St Microelectronics Alps Sas

Inventors

• Conte Antonino
• Maccarrone Agatino Massimo
• Tomaiuolo Francesco
• Jouanneau Thomas
• Russo Vincenzo

Classifications

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K19/018521

  of complementary type, e.g. CMOS · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C13/0028 Primary

  Word-line or row circuits · CPC title