Display substrate and display device

Patent metadata

Field	Value
Publication number	US-12494181-B2
Application number	US-202318578292-A
Country	US
Kind code	B2
Filing date	Feb 23, 2023
Priority date	Feb 23, 2023
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

A display substrate includes a base substrate, a first drive module, a second drive module, an array of sub-pixel circuits, rows of gate lines, and columns of data lines. A portion of sub-pixel circuits having a first color in the same row are electrically connected to one row of the gate line, another portion of sub-pixel circuits having the first color in the same row are electrically connected to another row of the gate line. The first drive module is electrically connected to a first end of the row of gate line and the second drive module is electrically connected to a second end of the another row of gate line. The first end and the second end are opposite ends. In the sub-pixel circuits located in the same row, at least two sub-pixel circuits at the same side of the data line are electrically connected to the data line.

First claim

What is claimed is:

1 . A display substrate, comprising:
a base substrate with a display area and a peripheral area surrounding the display area; a first drive module and a second drive module in the peripheral area; an array of sub-pixel circuits in the display area; the sub-pixel circuits having at least two colors including a first color and a second color; a plurality of rows of gate lines, with two rows of the gate lines between two adjacent rows of the sub-pixel circuits; and, a plurality of columns of data lines, with one column of the data line between every two columns of the sub-pixel circuits; wherein a portion of sub-pixel circuits having the first color located in the same row are electrically connected to one row of the gate line and are configured to write data voltage under control of a gate drive signal provided by the row of gate line; another portion of the sub-pixel circuits having the first color located in the same row are electrically connected to another row of gate line and are configured to receive data voltage under control of a gate drive signal provided by the another row of gate line; wherein a portion of sub-pixel circuits having the second color located in the same row are electrically connected to one row of the gate line and are configured to write data voltage under control of a gate drive signal provided by the row of gate line; another portion of the sub-pixel circuits having the second color located in the same row are electrically connected to another row of gate line and are configured to receive data voltage under control of a gate drive signal provided by the another row of gate line; the first drive module is electrically connected to a first end of the row of gate line and is configured to provide a gate drive signal to the row of gate line; the second drive module is electrically connected to a second end of the another row of gate line and is configured to provide a gate drive signal to the another row of gate line; the first end and the second end are opposite ends; in the sub-pixel circuits located in the same row, at least two sub-pixel circuits located at the same side of the data line are electrically connected to the data line.

2 . The display substrate according to claim 1 , wherein in the sub-pixel circuits located in the same row, at least two sub-pixel circuits are provided between two columns of the data lines, and the at least two sub-pixel circuits are electrically connected to one of the two columns of data lines.

3 . The display substrate according to claim 1 , wherein every two adjacent sub-pixel circuits having the same color located in the same row are electrically connected to different rows of gate lines, and each of the two adjacent sub-pixel circuits is configured to receive data voltage under control of a gate drive signal provided by a gate line connected with the each of the two adjacent sub-pixel circuits.

4 . The display substrate according to claim 1 , wherein the display substrate comprises N rows of sub-pixel circuits and 2N rows of gate lines; N is a positive integer;
odd-column sub-pixel circuits in the sub-pixel circuits having the same color located in the n-th row are electrically connected to the (2n−1)-th row of gate line, and even-column sub-pixel circuits in the sub-pixel circuits having the same color located in the n-th row are electrically connected to the 2n-th row of gate line; or, odd-column sub-pixel circuits in the sub-pixel circuits having the same color located in the n-th row are electrically connected to the 2n-th row of gate line, and even-column sub-pixel circuits in the sub-pixel circuits having the same color located in the n-th row are electrically connected to the (2n−1)-th row of gate line; n is a positive integer less than or equal to N.

5 . The display substrate according to claim 4 , wherein the first drive module comprises N stages of first drive circuits and the second drive module comprises N stages of second drive circuits;
the n-th stage first drive circuit is electrically connected to a first end of the (2n−1)-th row of gate line and is configured to provide a gate drive signal to the (2n−1)-th row of gate line; the n-th stage second drive circuit is electrically connected to a second end of the 2n-th row of gate line and is configured to provide the gate drive signal to the 2n-th row of gate lines.

6 . The display substrate according to claim 4 , wherein the first drive module comprises N stages of first drive circuits and the second drive module comprises N stages of second drive circuits;
the n-th stage first drive circuit is electrically connected to a second end of the (2n−1)-th row of gate line and is configured to provide a gate drive signal to the (2n−1)-th row of gate line; the n-th stage second drive circuit is electrically connected to a first end of the 2n-th row of gate line and is configured to provide a gate drive signal to the 2n-th row of gate lines.

7 . The display substrate according to claim 1 , wherein the sub-pixel circuit comprises a data writing transistor and a pixel electrode;
a gate of the data writing transistor is electrically connected to the gate line electrically connected to the sub-pixel circuit, a first pole of the data writing transistor is electrically connected to the data line, and the second pole of the data writing transistor is electrically connected to the pixel electrode.

8 . The display substrate according to claim 1 , comprising N rows and M columns of red sub-pixel circuits, N rows and M columns of green sub-pixel circuits, and N rows and M columns of blue sub-pixel circuits;
wherein the odd-column red sub-pixel circuits in the n-th row are electrically connected to the (2n−1)-th row of gate line, and the even-column red sub-pixel circuits in the n-th row are electrically connected to the 2n-th row of gate line; the odd-column green sub-pixel circuits in the n-th row are electrically connected to the 2n-th row of gate line, and the even-column green sub-pixel circuits in the n-th row are electrically connected to the (2n−1)-th row of gate line; the odd-column blue sub-pixel circuits in the n-th row are electrically connected to the (2n−1)-th row of gate line, and the even-column blue sub-pixel circuits in the n-th row are electrically connected to the 2n-th row of gate line; M and N are positive integers, n is a positive integer less than or equal to N.

9 . The display substrate according to claim 1 , comprising N rows and M columns of red sub-pixel circuits, N rows and M columns of green sub-pixel circuits, and N rows and M columns of blue sub-pixel circuits;
wherein the odd-column red sub-pixel circuits in the n-th row are electrically connected to the 2n-th row of gate line, and the even-column red sub-pixel circuits in the n-th row are electrically connected to the (2n−1)-th row of gate line; the odd-column green sub-pixel circuits in the n-th row are electrically connected to the (2n−1)-th row of gate line, and the even-column green sub-pixel circuits in the n-th row are electrically connected to the 2n-th row of gate line; the odd-column blue sub-pixel circuits in the n-th row are electrically connected to the 2n-th row of gate line, and the even-column blue sub-pixel circuits in the n-th row are electrically connected to the (2n−1)-th row of gate line; M and N are positive integers, n is a positive integer less than or equal to N.

10 . The display substrate according to claim 8 , wherein
the (2a−1)-th column red sub-pixel circuits in odd rows are electrically connected to the (4a−3)-th column data line, the (2a−1)-th column green sub-pixel circuits in odd rows are electrically connected to the (4a−3)-

Assignees

• Fuzhou Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Park Sangjin
• Chen Jixiang
• Wang Wenchao
• Wang Jinliang
• Fang Xin
• Xu Xu
• Xu Shanshan

Classifications

• G09G2320/0242

  Compensation of deficiencies in the appearance of colours · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0452

  Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components · CPC title

• G09G3/3648

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title