Pixel drive circuit and drive method thereof, and display apparatus

Patent metadata

Field	Value
Publication number	US-12494167-B2
Application number	US-202218028760-A
Country	US
Kind code	B2
Filing date	Mar 18, 2022
Priority date	Mar 18, 2022
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

Disclosed is a pixel drive circuit which is configured to drive a light emitting element to emit light and includes: a node control sub-circuit, configured to provide a signal of an initial signal terminal to a first node under control of a reset signal terminal, provide a signal of a second node to the first node under control of a scan signal terminal, and adjust a signal of the first node or the second node under control of a first control terminal; a drive sub-circuit, configured to provide a drive current to the second node under control of the first node and the third node; and a light emitting control sub-circuit, configured to provide a signal of a first power terminal to the third node and a signal of the second node to the fourth node under control of a light emitting control terminal.

First claim

The invention claimed is:

1 . A pixel drive circuit, configured to drive a light emitting element to emit light, comprising: a node control sub-circuit, a light emitting control sub-circuit, and a drive sub-circuit; wherein a working process of the pixel drive circuit comprises: an initialization stage, a data writing stage, and a light emitting stage;
the node control sub-circuit is electrically connected with a first power terminal, a reset signal terminal, an initial signal terminal, a first control terminal, a second control terminal, a scan signal terminal, a data signal terminal, a first node, a second node, a third node, and a fourth node respectively, and is configured to provide a signal from the initial signal terminal to the first node under control of a signal from the reset signal terminal, provide a signal from the initial signal terminal to the fourth node under control of a signal from the second control terminal, provide a signal from the second node to the first node and a signal from the data signal terminal to the third node under control of a signal from the scan signal terminal, and adjust a signal from the first node or the second node under control of a signal from the first control terminal; the drive sub-circuit is electrically connected with the first node, the second node, and the third node respectively, and is configured to provide a drive current to the second node under control of signals from the first node and the third node; the light emitting control sub-circuit is electrically connected with a light emitting control terminal, the first power terminal, the second node, the third node, and the fourth node respectively, and is configured to provide a signal from the first power terminal to the third node and a signal from the second node to the fourth node under control of a signal from the light emitting control terminal; and the light emitting element is electrically connected with the fourth node and a second power terminal respectively; wherein in the data writing stage and the light emitting stage, signals from the scan signal terminal and the first control terminal are mutually inverted signals, wherein the node control sub-circuit comprises: two first transistors connected in series, two second transistors connected in series, a fourth transistor, a seventh transistor, an eighth transistor, the drive sub-circuit comprises: a third transistor, and the light emitting control sub-circuit comprises: a fifth transistor and a sixth transistor; wherein the two second transistors and the eighth transistor have a same transistor type; and a width of a channel region of the eighth transistor is about 1 micron to 3 microns, and a length of the channel region of the eighth transistor is about 3 microns to 9 microns.

2 . The pixel drive circuit according to claim 1 , wherein the node control sub-circuit comprises: a first reset sub-circuit, a second reset sub-circuit, a compensation sub-circuit, a writing sub-circuit, and an energy storage sub-circuit;
the first reset sub-circuit is electrically connected with the reset signal terminal, the initial signal terminal, and the first node respectively, and is configured to provide the signal from the initial signal terminal to the first node under control of the signal from the reset signal terminal; the second reset sub-circuit is electrically connected with the second control terminal, the initial signal terminal, and the fourth node respectively, and is configured to provide the signal from the initial signal terminal to the fourth node under control of the signal from the second control terminal; the compensation sub-circuit is electrically connected with the first control terminal, the scan signal terminal, the first node, and the second node respectively, and is configured to provide the signal from the second node to the first node under control of the signal from the scan signal terminal, and adjust the signal from the first node or the second node under control of the signal from the first control terminal; the writing sub-circuit is electrically connected with the scan signal terminal, the data signal terminal, and the third node respectively, and is configured to provide a signal from the data signal terminal to the third node under control of the signal from the scan signal terminal; and the energy storage sub-circuit is electrically connected with the first node and the first power terminal respectively, and is configured to store a voltage difference between the first node and the first power terminal.

3 . The pixel drive circuit according to claim 2 , wherein the first reset sub-circuit comprises: the two first transistors connected in series, and the second reset sub-circuit comprises: the seventh transistor;
a control electrode of a first transistor is electrically connected with the reset signal terminal, a first electrode of the first transistor is electrically connected with the initial signal terminal, and a second electrode of the first transistor is electrically connected with a first electrode of a second first transistor; a control electrode of the second first transistor is electrically connected with the reset signal terminal, and a second electrode of the second first transistor is electrically connected with the first node; and a control electrode of the seventh transistor is electrically connected with the second control terminal, a first electrode of the seventh transistor is electrically connected with the initial signal terminal, and a second electrode of the seventh transistor is electrically connected with the fourth node.

4 . The pixel drive circuit according to claim 2 , wherein the compensation sub-circuit comprises: the two second transistors connected in series and the eighth transistor;
a control electrode of a first second transistor is electrically connected with the scan signal terminal, a first electrode of the first second transistor is electrically connected with the second node, and a second electrode of the first second transistor is electrically connected with a first electrode of a second second transistor; a control electrode of the second second transistor is electrically connected with the scan signal terminal, and a second electrode of the second second transistor is electrically connected with a first electrode of the eighth transistor; and a control electrode of the eighth transistor is electrically connected with the first control terminal, and a second electrode of the eighth transistor is electrically connected with the first node and a first electrode of the eighth transistor respectively.

5 . The pixel drive circuit according to claim 2 , wherein the compensation sub-circuit comprises: the two second transistors connected in series and the eighth transistor;
a control electrode of a first second transistor is electrically connected with the scan signal terminal, a first electrode of the first second transistor is electrically connected with a second electrode of the eighth transistor, and a second electrode of the first second transistor is electrically connected with a first electrode of a second second transistor; a control electrode of the second second transistor is electrically connected with the scan signal terminal, and a second electrode of the second second transistor is electrically connected with the first node; and a control electrode of the eighth transistor is electrically connected with the first control terminal, and a first electrode of the eighth transistor is electrically connected with the second node and the second electrode of the eighth transistor respectively.

6 . The pixel drive circuit according to claim 2 , wherein the writing sub-circuit comprises: the fourth transistor, and the energy storage sub-circuit compr

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Ren Huaisen
• Guo Yonglin
• Wang Miao
• Gao Tao

Classifications

• G09G3/3208

  organic, e.g. using organic light-emitting diodes [OLED] · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title