Device and methods for functional descriptor-based DMA controller

Patent metadata

Field	Value
Publication number	US-12493570-B2
Application number	US-202418621183-A
Country	US
Kind code	B2
Filing date	Mar 29, 2024
Priority date	Sep 26, 2023
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

A microcontroller may include a DMA controller, a pattern matching circuit and a memory. The DMA controller may read a first descriptor word in the memory at a location addressed by a first descriptor pointer, and may move an input word from a location in the memory addressed by a source payload pointer to a location in the memory addressed by a destination payload pointer. The pattern matching circuit may perform a pattern matching operation based on the input word and one or more register values. The first descriptor pointer may be modified based on the results of the pattern matching circuit and may generate a second descriptor pointer value.

First claim

The invention claimed is:

1 . A microcontroller comprising:
a DMA controller circuit comprising a data buffer and a pattern matching circuit; a memory coupled to the DMA controller, the memory comprising a descriptor table; wherein the DMA controller circuit:
reads data into the data buffer from a location in the descriptor table, the location specified by a first descriptor pointer;
reads an input word within the memory at a location specified by a source payload pointer and writes the input word to an address specified by a destination payload pointer;
performs a pattern matching operation in the pattern matching circuit based on the input word and one or more register values to generate a pattern matching result;
modifies the first descriptor pointer based on the value of the first descriptor pointer and the result, of the pattern matching operation to generate a second descriptor pointer;
updates the first descriptor pointer in the descriptor table at the first descriptor pointer, and
wherein the descriptor table comprises a source descriptor table, the source descriptor table comprising the source payload pointer, a size field, a first descriptor pointer offset and a second descriptor pointer offset.

2 . The microcontroller as claimed in claim 1 , the pattern matching operation comprising a bit-wise AND operation based on the input word, a mask word and a pattern word.

3 . The microcontroller as claimed in claim 2 , the pattern matching circuit to add the first descriptor pointer offset to the first descriptor pointer based on a first result of the pattern matching operation.

4 . The microcontroller as claimed in claim 2 , the pattern matching circuit to add the second descriptor pointer offset to the first descriptor pointer based on a second result of the pattern matching operation.

5 . The microcontroller as claimed in claim 1 , the descriptor table comprising a destination descriptor table, the destination descriptor table comprising a destination payload pointer, a size field, a first descriptor pointer offset and a second descriptor pointer offset.

6 . The microcontroller as claimed in claim 5 , the pattern matching operation comprising a bit-wise AND operation based on the input word, a mask word and a pattern word.

7 . The microcontroller as claimed in claim 6 , the pattern matching circuit to add the first descriptor pointer offset to the first descriptor pointer based on a first result of the pattern matching operation.

8 . The microcontroller as claimed in claim 6 , the pattern matching circuit to add the second descriptor pointer offset to the first descriptor pointer based on a second result of the pattern matching operation.

9 . The microcontroller as claimed in claim 1 , the source payload pointer comprising a register value.

10 . The microcontroller as claimed in claim 5 , the source payload pointer comprising contents of the destination descriptor table.

11 . The microcontroller as claimed in claim 5 , the destination payload pointer comprising a register value.

12 . A method comprising:
reading a descriptor table in a memory at an address specified by a first descriptor pointer and reading a descriptor word into a data buffer; reading an input word within the memory based on the contents of the data buffer; performing a pattern matching operation based on the input word and one or more register values to generate a pattern matching result; writing the input word to the memory based on the contents of the data buffer; modifying the first descriptor pointer based on the value of the first descriptor pointer and the result of the pattern matching operation; and updating the first descriptor pointer in the descriptor table at the address specified by the first descriptor pointer.

13 . The method as claimed in claim 12 , the pattern matching operation comprising a bit-wise AND operation based on the input word, a mask word and a pattern word.

14 . The method as claimed in claim 12 , the pattern matching circuit to add a first descriptor pointer offset to the first descriptor pointer based on a first result of the pattern matching operation.

15 . The method as claimed in claim 12 , the pattern matching circuit to add a second descriptor pointer offset to the first descriptor pointer based on a second result of the pattern matching operation.

16 . The method as claimed in claim 12 , the updating the first descriptor pointer comprising incrementing or decrementing the payload pointer.

Assignees

• Microchip Tech Inc

Inventors

• Yuenyongsgool Yong
• Reiter Andreas
• Bowling Stephen
• Alkhimenok Anton
• Phoenix Tim

Classifications

• G06F13/1673

  using buffers · CPC title

• G06F7/764

  Masking · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title