Tiling display apparatus

Patent metadata

Field	Value
Publication number	US-12493441-B2
Application number	US-202418628218-A
Country	US
Kind code	B2
Filing date	Apr 5, 2024
Priority date	Dec 31, 2021
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

A tiling display apparatus includes a plurality of display modules connected to one another through a first interface circuit and a second interface circuit and a set board receiving a defect occurrence and position signal, generated in a broken-down module of the plurality of display modules, from the broken module through the first interface circuit in a first period, generating a defect recognition completion signal in a second period succeeding the first period, and transferring the defect recognition completion signal to the broken-down module through the second interface circuit in the second period.

First claim

What is claimed is:

1 . A tiling display apparatus comprising:
a plurality of display modules connected to one another through a first interface circuit and a second interface circuit, the plurality of display modules including a broken-down module having a timing controller configured to determine that the broken-down module is broken and output a defect occurrence and position signal responsive to the determination; and a set board receiving the defect occurrence and position signal output from the broken-down module through the first interface circuit in a first period, generating a defect recognition completion signal in a second period succeeding the first period that acknowledges a receipt of the defect occurrence and position signal responsive to receiving the defect occurrence and position signal, and transferring the defect recognition completion signal to the broken-down module through the second interface circuit in the second period, wherein each of the defect occurrence and position signal and the defect recognition completion signal is a pulse signal which swings between a high logic voltage and a low logic voltage, and wherein the set board further receives a defect history signal of the broken-down module from the broken-down module through the first interface circuit in a third period succeeding the second period.

2 . The tiling display apparatus of claim 1 , wherein the defect occurrence and position signal comprises a first falling edge and one or more first rising edges arranged next to the first falling edge, and the defect recognition completion signal comprises a second rising edge.

3 . The tiling display apparatus of claim 2 , wherein, in the first period, the set board recognizes occurrence of a defect of the broken-down module based on the first falling edge of the defect occurrence and position signal, counts the one or more first rising edges of the defect occurrence and position signal, and recognizes a position of the broken-down module based on a number of first rising edges, and
in the second period, the broken-down module recognizes a defect recognition completion state of the set board based on the second rising edge of the defect recognition completion signal.

4 . The tiling display apparatus of claim 2 , wherein a number of first rising edges varies based on a connection position of the broken-down module of the plurality of display modules.

5 . The tiling display apparatus of claim 2 , wherein a number of first rising edges corresponds to a connection sequence, based on the second interface circuit, of the broken-down module of the plurality of display modules.

6 . The tiling display apparatus of claim 1 , wherein the defect history signal is a pulse signal that swings between the high logic voltage and the low logic voltage, and the defect history signal comprises one or more third rising edges.

7 . The tiling display apparatus of claim 6 , wherein the set board counts the one or more third rising edges of the defect history signal and recognizes, as a defect history of the broken-down module, one piece of defect candidate information of a breakdown diagnosis list based on a number of third rising edges.

8 . The tiling display apparatus of claim 7 , wherein the breakdown diagnosis list of the broken-down module comprises pieces of defect candidate information having different setting sequences, and
the number of third rising edges corresponds to a setting sequence, of a piece of defect candidate information corresponding to a defect history of the broken-down module, among the pieces of the defect candidate information.

9 . The tiling display apparatus of claim 1 , wherein each of the first interface circuit and the second interface circuit is implemented with a serial peripheral interface.

10 . The tiling display apparatus of claim 1 , wherein the defect history signal is indicative of a type of historical defect that previously occurred in the broken-down module from a plurality of different types of historical defects.

11 . A tiling display apparatus comprising:
a set board; and a plurality of display modules connected to one another through a first interface circuit and a second interface circuit, wherein at least one of the plurality of display modules comprises:
a timing controller configured to: determine that the display module is broken, generate a defect occurrence and position signal responsive to determining that the display module is broken, and output the defect occurrence and position signal to the set board through the first interface circuit in a first period, and receive, from the set board, a defect recognition completion signal that is generated by the set board and acknowledges a receipt of the defect occurrence and position signal by the set board responsive to receiving the defect occurrence and position signal through the second interface circuit in a second period succeeding the first period,
wherein each of the defect occurrence and position signal and the defect recognition completion signal is a pulse signal which swings between a high logic voltage and a low logic voltage, and
wherein the timing controller is further configured to generate a defect history signal of the display module and transfer the defect history signal to the set board through the first interface circuit in a third period succeeding the second period.

Assignees

• Lg Display Co Ltd

Inventors

• Park Sang Woo
• Kim Tae Gung

Classifications

• G09G2360/04

  Display device controller operating with a plurality of display units · CPC title

• G09G2330/12

  Test circuits or failure detection circuits included in a display system, as permanent part thereof · CPC title

• G06F2201/86

  Event-based monitoring · CPC title

• G09G2300/026

  Video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions · CPC title

• G09G2330/10

  Dealing with defective pixels · CPC title