Semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-12490469-B2
Application number	US-202318164600-A
Country	US
Kind code	B2
Filing date	Feb 5, 2023
Priority date	Oct 25, 2022
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

A semiconductor device includes a substrate, and a first transistor disposed on the substrate. The first transistor includes a first channel layer, a magnesium oxide layer, a first gate electrode, a first gate dielectric and first source/drain electrodes. A crystal orientation of the first channel layer is <100> or <110>. The magnesium oxide layer is located below the first channel layer and in contact with the first channel layer. The first gate electrode is located over the first channel layer. The first gate dielectric is located in between the first channel layer and the first gate electrode. The first source/drain electrodes are disposed on the first channel layer.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate; a first transistor disposed on the substrate, wherein the first transistor comprises:
a first channel layer, wherein a crystal orientation of the first channel layer is <100> or <110>;
a magnesium oxide layer located below the first channel layer and in contact with the first channel layer;
a first gate electrode located over the first channel layer;
a first gate dielectric located in between the first channel layer and the first gate electrode; and
first source/drain electrodes disposed on the first channel layer; and
a second transistor disposed on the substrate, wherein the second transistor comprises:
a second channel layer, wherein the second channel layer comprises indium-gallium-zinc-oxide (IGZO);
second source/drain electrodes disposed on the second channel layer;
a second gate electrode disposed on the second channel layer; and
a second gate dielectric located in between the second channel layer and the second gate electrode.

2 . The semiconductor device according to claim 1 , wherein a crystal orientation of the magnesium oxide layer is the same as the crystal orientation of the first channel layer.

3 . The semiconductor device according to claim 1 , further comprising a bottom metal layer located below and in contact with the magnesium oxide layer.

4 . The semiconductor device according to claim 3 , wherein the bottom metal layer comprises a material selected from the group consisting of iron (Fe), cobalt-iron-boron (CoFeB) and nickel-chromium (NiCr).

5 . The semiconductor device according to claim 1 , wherein the first channel layer comprises a material selected from the group consisting of germanium (Ge), nickel oxide (NiO), and tellurium (Te).

6 . The semiconductor device according to claim 5 , wherein the first channel layer is germanium (Ge).

7 . A semiconductor device, comprising:
a substrate; an interconnection structure disposed on the substrate, wherein the interconnection structure comprises:
a plurality of dielectric layers and a plurality of conductive layers alternately stacked;
a plurality of p-type transistors embedded in the plurality of dielectric layers, wherein the plurality of p-type transistors comprises a crystalline channel layer, and a magnesium oxide layer located below the crystalline channel layer;
a plurality of n-type transistors embedded in the plurality of dielectric layers, wherein the plurality of n-type transistors comprises an amorphous channel layer; and
a plurality of conductive terminals disposed on and electrically connected to the interconnection structure.

8 . The semiconductor device according to claim 7 , wherein sidewalls of the crystalline channel layer are aligned with sidewalls of the magnesium oxide layer.

9 . The semiconductor device according to claim 7 , wherein the crystalline channel layer is a single crystal germanium (Ge) layer.

10 . The semiconductor device according to claim 7 , wherein the plurality of p-type transistors further comprises:
first source/drain electrodes located on the crystalline channel layer; a first gate dielectric disposed on the crystalline channel layer and in between the first source/drain electrodes; and a first gate electrode disposed on the first gate dielectric.

11 . The semiconductor device according to claim 7 , wherein the plurality of p-type transistors further comprises:
first source/drain electrodes located on the crystalline channel layer; a first gate dielectric disposed below the magnesium oxide layer; and a first gate electrode disposed below the first gate dielectric.

12 . The semiconductor device according to claim 7 , wherein the plurality of p-type transistors further comprise an iron (Fe) layer located below the magnesium oxide layer.

13 . The semiconductor device according to claim 12 , wherein a crystal orientation of the magnesium oxide layer is the same as a crystal orientation of the iron (Fe) layer and a crystal orientation of the crystalline channel layer.

14 . The semiconductor device according to claim 7 , wherein an amount of the plurality of n-type transistors located in the interconnection structure is greater than an amount of the plurality of p-type transistors located in the interconnection structure.

15 . A method of forming a semiconductor device, comprising:
forming a first transistor on a substrate, wherein the first transistor is formed by:
forming a magnesium oxide layer on the substrate;
forming a first channel layer on the substrate, wherein the magnesium oxide layer is located below the first channel layer and in contact with the first channel layer, and a crystal orientation of the first channel layer is <100> or <110>;
forming a first gate electrode over the first channel layer;
forming a first gate dielectric in between the first channel layer and the first gate electrode; and
forming first source/drain electrodes on the first channel layer; and
forming a second transistor on the substrate, wherein the second transistor is formed by:
forming a second channel layer, wherein the second channel layer comprises indium-gallium-zinc-oxide (IGZO);
forming second source/drain electrodes disposed on the second channel layer;
forming a second gate electrode disposed on the second channel layer; and
forming a second gate dielectric in between the second channel layer and the second gate electrode.

16 . The method according to claim 15 , wherein the magnesium oxide layer is formed with a crystal orientation that is the same as the crystal orientation of the first channel layer.

17 . The method according to claim 15 , further comprising forming a bottom metal layer on the substrate prior to forming the magnesium oxide layer, and forming the magnesium oxide layer directly on the bottom metal layer.

18 . The method according to claim 16 , wherein the bottom metal layer comprises a material selected from the group consisting of iron (Fe), cobalt-iron-boron (CoFeB) and nickel-chromium (NiCr).

19 . The method according to claim 15 , wherein the first channel layer is formed as a single crystal germanium (Ge) layer.

20 . The semiconductor device according to claim 1 , wherein sidewalls of the first channel layer are aligned with sidewalls of the first source/drain electrodes.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Manufacuturing Company Ltd

Inventors

• Goto Ken-Ichi
• Wu Cheng-Yi

Classifications

• H10P14/3466

  Crystal orientation · CPC title

• H10P14/3458

  Monocrystalline · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3402

  characterised by the chemical composition · CPC title