Dielectric sidewall features for tuning thin film transistor (TFT) parasitics

Patent metadata

Field	Value
Publication number	US-12490460-B2
Application number	US-202217742631-A
Country	US
Kind code	B2
Filing date	May 12, 2022
Priority date	May 12, 2022
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

Techniques are provided herein for forming transistor devices with reduced parasitic capacitance, such as transistors used in a memory structure. In an example, a given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT), and the storage device may include a capacitor. Any of the given TFTs may include a dielectric liner extending along sidewalls of the TFT. The TFT includes a recess (e.g., a dimple) that extends laterally inwards toward a midpoint of a semiconductor region of the TFT. The dielectric liner thus also pinches or otherwise extends inward. This pinched-in dielectric liner may reduce parasitic capacitance between the contacts of the TFT and the gate electrode of the TFT. The pinched-in dielectric liner may also protect the contacts from forming too deep into the semiconductor region.

First claim

What is claimed is:

1 . An integrated circuit, comprising:
a gate electrode; a gate dielectric on the gate electrode; a semiconductor region on the gate dielectric; a conductive contact that contacts at least a portion of the semiconductor region; and a dielectric liner that extends along a sidewall of at least the gate electrode, the gate dielectric, and the semiconductor region, wherein the portion of the dielectric liner on the sidewall of the semiconductor region extends inwards towards a midpoint of the semiconductor region.

2 . The integrated circuit of claim 1 , wherein the dielectric liner extends around a perimeter of each of the gate electrode, the gate dielectric, and the semiconductor region.

3 . The integrated circuit of claim 1 , further comprising one or more dielectric layers on the semiconductor region, wherein the dielectric liner further extends along a sidewall of the one or more dielectric layers.

4 . The integrated circuit of claim 1 , wherein the dielectric liner comprises hafnium and oxygen.

5 . The integrated circuit of claim 1 , wherein at least a portion of the conductive contact is touching the dielectric liner where the dielectric liner extends inwards.

6 . The integrated circuit of claim 1 , wherein a width of a bottom surface of the semiconductor region is greater than a width of a bottom surface of the conductive contact.

7 . The integrated circuit of claim 1 , wherein each of the gate electrode, the gate dielectric, the semiconductor region on the gate dielectric, the conductive contact, and the dielectric liner structure is part of a transistor structure that is part of an array of transistor structures within an interconnect structure.

8 . A printed circuit board comprising the integrated circuit of claim 1 .

9 . An electronic device, comprising:
a chip package having one or more dies, wherein at least one of the one or more dies includes
a plurality of semiconductor devices;
an interconnect region above the plurality of semiconductor devices, the interconnect region comprising a plurality of stacked interconnect layers; and
a thin film transistor (TFT) structure within an interconnect layer of the plurality of stacked interconnect layers, the TFT structure comprising
a gate electrode,
a gate dielectric on the gate electrode,
a semiconductor region on the gate dielectric,
a conductive contact that contacts at least a portion of the semiconductor region, and
a dielectric liner that extends along a sidewall of at least the gate electrode, the gate dielectric, and the semiconductor region, wherein the portion of the dielectric liner on the sidewall of the semiconductor region laterally extends towards a midpoint of the semiconductor region.

10 . The electronic device of claim 9 , wherein the dielectric liner extends around a perimeter of each of the gate electrode, gate dielectric, and semiconductor region.

11 . The electronic device of claim 9 , wherein at least a portion of the conductive contact is partially on or otherwise touching the dielectric liner.

12 . The electronic device of claim 9 , wherein a width of a bottom surface of the semiconductor region is greater than a width of a bottom surface of the conductive contact.

13 . The electronic device of claim 9 , wherein the TFT structure is one TFT structure of an array of TFT structures within the interconnect layer.

14 . The electronic device of claim 9 , further comprising a printed circuit board, wherein the chip package is coupled to the printed circuit board.

15 . An integrated circuit, comprising:
a plurality of semiconductor devices; an interconnect region above the plurality of semiconductor devices, the interconnect region comprising a plurality of stacked interconnect layers; and a thin film transistor (TFT) structure within an interconnect layer of the plurality of stacked interconnect layers, the TFT structure comprising
a gate electrode,
a gate dielectric on the gate electrode,
a semiconductor region on the gate dielectric, the semiconductor region having a lateral recess along a sidewall of the semiconductor region;
a dielectric liner that extends along a sidewall of at least the gate electrode, the gate dielectric, and the semiconductor region, such that a portion of the dielectric liner is within the lateral recess of the semiconductor region; and
a conductive contact that contacts at least a portion of a top surface of the semiconductor region and at least a portion of the portion of the dielectric liner within the lateral recess.

16 . The integrated circuit of claim 15 , wherein the dielectric liner extends around a perimeter of each of the gate electrode, gate dielectric, and semiconductor region.

17 . The integrated circuit of claim 15 , further comprising one or more dielectric layers on the semiconductor region, wherein the dielectric liner further extends along a sidewall of the one or more dielectric layers.

18 . The integrated circuit of claim 15 , wherein a width of a bottom surface of the semiconductor region is greater than a width of a bottom surface of the conductive contact.

19 . The integrated circuit of claim 15 , wherein the TFT structure is one TFT structure of an array of TFT structures within the interconnect layer.

20 . A printed circuit board comprising the integrated circuit of claim 15 .

Assignees

• Intel Corp

Inventors

• Tan Cheng
• Huang Yu-Wen
• Chuang Hui-Min
• Weng Xiaojun
• Mehta Nikhil J
• Gardiner Allen B
• Zhou Shu
• Jen Timothy
• Sharma Abhishek Anil
• Le Van H
• Lajoie Travis W
• Sell Bernhard

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title

• H10B12/05

  Making the transistor · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/675

  Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium · CPC title