Integrated assemblies having transistors configured for high-voltage applications, and methods of forming integrated assemblies

Patent metadata

Field	Value
Publication number	US-12490452-B2
Application number	US-202418653289-A
Country	US
Kind code	B2
Filing date	May 2, 2024
Priority date	Jul 2, 2020
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

Some embodiments include an integrated assembly having a first gate operatively adjacent a channel region, a first source/drain region on a first side of the channel region, and a second source/drain region on an opposing second side of the channel region. The first source/drain region is spaced from the channel region by an intervening region. The first and second source/drain regions are gatedly coupled to one another through the channel region. A second gate is adjacent a segment of the intervening region and is spaced from the first gate by an insulative region. A lightly-doped region extends across the intervening region and is under at least a portion of the first source/drain region. Some embodiments include methods of forming integrated assemblies.

First claim

We claim:

1 . An integrated assembly, comprising:
a first gate operatively adjacent a channel region; a first source/drain region on a first side of the channel region, and a second source/drain region on a second side of the channel region, with the second side being in opposing relation to the first side; the first source/drain region being spaced from the channel region by an intervening region; the first and second source/drain regions being gatedly coupled to one another through the channel region; a second gate adjacent a segment of the intervening region and spaced from the first gate by an insulative region; a lightly-doped region extending across the intervening region and being under at least a portion of the first source/drain region; and wherein the intervening region is a first intervening region, and further comprising:
a second intervening region between the second source/drain region and the channel region; and
a third gate adjacent a segment of the second intervening region; and
wherein the second gate is one gate or a plurality of second gates which are spaced apart from one another over segments of the first intervening region, and wherein the third gate is one gate or of a plurality of third gates which are spaced apart from one another over segments of the second intervening region; and wherein the third gate comprise a different number of gates than the second gate.

2 . The integrated assembly of claim 1 wherein the first gate is coupled with driver circuitry configured to selectively provide voltage to the first gate to selectively induce an electric field within the channel region and thereby selectively transition the channel region between a first operational mode that couples the first and second source/drain regions with one another and a second operational mode that does not couple the first and second source/drain regions with one another; and wherein the second and third gates are held at a static voltage level during all operational modes of the channel region.

3 . The integrated assembly of claim 1 wherein the first gate is coupled with driver circuitry configured to selectively provide voltage to the first gate to selectively induce an electric field within the channel region and thereby selectively transition the channel region between a first operational mode that couples the first and second source/drain regions with one another and a second operational mode that does not couple the first and second source/drain regions with one another; and wherein the second and third gates electrically float during all operational modes of the channel region.

4 . The integrated assembly of claim 1 wherein the first gate is coupled with driver circuitry configured to selectively provide voltage to the first gate to selectively induce an electric field within the channel region and thereby selectively transition the channel region between a first operational mode that couples the first and second source/drain regions with one another and a second operational mode that does not couple the first and second source/drain regions with one another; and wherein the second and third gates are also coupled with the driver circuitry.

5 . An integrated assembly, comprising:
a first gate coupled to a voltage and operatively adjacent a channel region; a first source/drain region on a first side of the channel region along a first direction, and a second source/drain region on a second side of the channel region in the first direction; a second gate over the first side and laterally spaced apart from a first sidewall of the first gate in the first direction; and a third gate over the second side and laterally spaced apart from a second sidewall of the first gate in the first direction, at least one of the second and third gate coupled to a voltage different from the voltage of the first gate.

6 . The integrated assembly of claim 5 wherein both the second and third gates are coupled to voltages different from the voltage of the first gate.

7 . The integrated assembly of claim 5 wherein the voltage of the at least one of the second and third gate comprises a reference voltage.

8 . The integrated assembly of claim 5 wherein both the second and third gates are coupled to voltages different from the voltage of the first gate, the voltage of the second gate is different from the voltage of the third gate.

9 . The integrated assembly of claim 5 wherein both the second and third gates are coupled to voltages different from the voltage of the first gate, the voltage of the second gate is the same as the voltage of the third gate.

10 . The integrated assembly of claim 5 wherein the voltage of the at least one of the second and third gate comprises a reference voltage of at least one of Vdd, Vss and Vdd/2.

11 . An integrated assembly, comprising:
a first gate over a first gate dielectric and operatively adjacent a channel region; a first source/drain region on a first side of the channel region along a first direction, and a second source/drain region on a second side of the channel region in the first direction; a second gate over the first side, laterally spaced apart from a first sidewall of the first gate in the first direction and against a second gate dielectric that is a different structure from the first gate dielectric; and a third gate over the second side, laterally spaced apart from a second sidewall of the first gate in the first direction and against a third gate dielectric that is a different structure from the first gate dielectric.

12 . The integrated assembly of claim 11 wherein the third gate dielectric is a different structure from the second gate dielectric.

13 . The integrated assembly of claim 11 further comprising an insulative material between the first and second gate dielectrics.

14 . The integrated assembly of claim 13 wherein the insulative material comprises a composition of material different from a composition of material of the first and second gate dielectrics.

15 . The integrated assembly of claim 13 wherein the insulative material comprises silicon nitride.

16 . The integrated assembly of claim 13 wherein the insulative material comprises silicon nitride and silicon oxide.

17 . The integrated assembly of claim 13 wherein the insulative material comprises silicon nitride, and the first and second gate dielectrics comprise silicon oxide.

18 . An integrated assembly, comprising:
a first gate operatively adjacent a channel region; a first source/drain region on a first side of the channel region, and a second source/drain region on a second side of the channel region, with the second side being in opposing relation to the first side; the first source/drain region being spaced from the channel region by an intervening region; the first and second source/drain regions being gatedly coupled to one another through the channel region; a second gate adjacent a segment of the intervening region and spaced from the first gate by an insulative region; a lightly-doped region extending across the intervening region and being under at least a portion of the first source/drain region; and wherein the intervening region is a first intervening region, and further comprising:
a second intervening region between the second source/drain region and the channel region; and
a third gate adjacent a segment of the second intervening region; and
wherein the first gate is coupled with driver circuitry configured to selectively provide voltage to the first gate to selectively induce

Assignees

• Micron Technology Inc

Inventors

• Shafi Zia A
• Laurin Luca
• Panda Durga P
• Vigano′ Sara

Classifications

• H10D84/0181

  Manufacturing their gate insulating layers · CPC title

• H10D84/0174

  the gate conductors being silicided · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/017

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title