Continuous-time data converter with digital multi-stage noise shaping subconverter

Patent metadata

Field	Value
Publication number	US-12489457-B2
Application number	US-202318472752-A
Country	US
Kind code	B2
Filing date	Sep 22, 2023
Priority date	Sep 22, 2023
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

In accordance with an embodiment, a continuous-time delta-sigma analog-to-digital converter (ADC) includes: a continuous-time loop filter having an input coupled to an input of the continuous-time delta-sigma ADC; a multi-bit quantizer coupled to an output of the continuous-time loop filter; a 1-bit or 1.5 bit digital delta-sigma modulator having an input coupled to an output of the multi-bit quantizer and an output coupled to an input of the continuous-time loop filter; and a multi-bit digital delta-sigma modulator configured to requantize quantization error of the 1-bit or 1.5-bit digital delta-sigma modulator and having an output coupled to the input of the continuous-time loop filter and to an input of the 1-bit or 1.5-bit digital delta-sigma modulator.

First claim

What is claimed is:

1 . A continuous-time delta-sigma analog-to-digital converter (ADC) comprising:
a continuous-time loop filter having an input coupled to an input of the continuous-time delta-sigma ADC; a multi-bit quantizer coupled to an output of the continuous-time loop filter; a 1-bit or 1.5-bit digital delta-sigma modulator having a first input coupled to an output of the multi-bit quantizer and an output coupled to an input of the continuous-time loop filter; and a multi-bit digital delta-sigma modulator configured to requantize quantization error of the 1-bit or 1.5-bit digital delta-sigma modulator and having an output coupled to the input of the continuous-time loop filter and to an input of the 1-bit or 1.5-bit digital delta-sigma modulator, wherein the output of the multi-bit digital delta-sigma modulator is configured to provide digital values to the input of the 1-bit or 1.5-bit digital delta-sigma modulator via an all digital feedback path.

2 . The continuous-time delta-sigma ADC of claim 1 , wherein the 1-bit or 1.5-bit digital delta-sigma modulator and the multi-bit digital delta-sigma modulator each comprises a second order modulator.

3 . The continuous-time delta-sigma ADC of claim 1 , further comprising:
a first digital-to-analog converter coupled between the output of the 1-bit or 1.5-bit digital delta-sigma modulator and the input of the continuous-time loop filter; and a second digital-to-analog converter coupled between the output of the multi-bit digital delta-sigma modulator and the input of the continuous-time loop filter.

4 . The continuous-time delta-sigma ADC of claim 3 , wherein the second digital-to-analog converter comprises a finite impulse response (FIR) filter coupled to a plurality of digital-to-analog converters.

5 . The continuous-time delta-sigma ADC of claim 1 , wherein:
the 1-bit or 1.5-bit digital delta-sigma modulator comprises a 1-bit or 1.5-bit quantizer; and the continuous-time delta-sigma ADC further comprises a first subtractor having a first input coupled to an input of the 1-bit or 1.5-bit quantizer, and a second input coupled to an output of the 1-bit or 1.5-bit quantizer, and an output coupled to an input of the multi-bit digital delta-sigma modulator.

6 . The continuous-time delta-sigma ADC of claim 5 , wherein the 1-bit or 1.5-bit digital delta-sigma modulator comprises a second subtractor having a first input coupled to the output of the 1-bit or 1.5-bit quantizer, a second input coupled to an output of the multi-bit digital delta-sigma modulator, and an output coupled to an input of a loop filter of the 1-bit or 1.5-bit digital delta-sigma modulator.

7 . The continuous-time delta-sigma ADC of claim 1 , wherein the continuous-time loop filter comprises a plurality of continuous-time integrators.

8 . The continuous-time delta-sigma ADC of claim 7 , wherein the continuous-time delta-sigma ADC comprises a cascade of integrators with distributed feedback (CIFB) structure.

9 . The continuous-time delta-sigma ADC of claim 7 , further comprising a decimation filter coupled to the output of the multi-bit quantizer.

10 . A method of operating a continuous-time delta-sigma analog-to-digital converter (ADC), the method comprising:
filtering an analog input signal using a continuous-time loop filter; quantizing an output of the continuous-time loop filter using a multi-bit quantizer to form a quantized signal; feeding back the quantized signal to an input of the continuous-time loop filter via a 1-bit or 1.5-bit digital delta-sigma modulator; subtracting a quantization error of the 1-bit or 1.5-bit digital delta-sigma modulator from the input of the continuous-time loop filter using a multi-bit digital delta-sigma modulator; and feeding back a digital signal from an output of the multi-bit digital delta-sigma modulator to an input of the 1-bit or 1.5-bit digital delta-sigma modulator via an all digital feedback path.

11 . The method of claim 10 , further comprising:
converting an output of the 1-bit or 1.5-bit digital delta-sigma modulator from a first digital signal to a first analog signal using a first digital-to-analog converter; and converting the output of the multi-bit digital delta-sigma modulator from the digital signal to a second analog signal using a second digital-to-analog converter.

12 . The method of claim 10 , wherein subtracting the quantization error of the 1-bit or 1.5-bit digital delta-sigma modulator from the input of the continuous-time loop filter using the multi-bit digital delta-sigma modulator comprises:
determining a difference between an output of a 1-bit or 1.5-bit quantizer of the 1-bit or 1.5-bit digital delta-sigma modulator and an input of the 1-bit or 1.5-bit quantizer to form a first difference signal; and modulating the first difference signal using the multi-bit digital delta-sigma modulator.

13 . The method of claim 12 , wherein feeding back the digital signal output from the output of the multi-bit digital delta-sigma modulator to the input of the 1-bit or 1.5-bit digital delta-sigma modulator comprises:
determining a difference between the digital signal output from the multi-bit digital delta-sigma modulator and the output of the 1-bit or 1.5-bit quantizer of the 1-bit or 1.5-bit digital delta-sigma modulator to form a second difference signal; and providing the second difference signal to an input of a loop filter of the 1-bit or 1.5-bit digital delta-sigma modulator.

14 . The method of claim 10 , wherein filtering the analog input signal using the continuous-time loop filter comprises integrating the analog input signal using a plurality of integrators.

15 . The method of claim 14 , further comprising feeding back the quantized signal to respective inputs of the plurality of integrators.

16 . The method of claim 10 , further comprising decimating the quantized signal using a decimation filter.

17 . A circuit comprising:
a delta-sigma modulator disposed on a monolithic semiconductor substrate, the delta-sigma modulator comprising:
an analog loop filter having an input coupled to an analog input node,
a quantizer coupled to an output of the analog loop filter, and
a sturdy multi-stage noise shaping digital-to-analog converter (DAC) coupled between an output of the quantizer and the input of the analog loop filter, the sturdy multi-stage noise shaping DAC comprising a 1-bit or 1.5-bit digital delta-sigma modulator, a multi-bit digital delta-sigma modulator configured to modulate a quantization error of the 1-bit or 1.5-bit digital delta-sigma modulator, and an all digital feedback path configured to route a digital signal at a digital output of the multi-bit digital delta-sigma modulator to a digital input of the 1-bit or 1.5-bit digital delta-sigma modulator; and
a functional circuit disposed on the monolithic semiconductor substrate and coupled to an output of the delta-sigma modulator.

18 . The circuit of claim 17 , further comprising a first finite impulse response (FIR) digital to analog converter coupled between the output of the multi-bit digital delta-sigma modulator and the input of the analog loop filter.

19 . The circuit of claim 17 , wherein the analog loop filter comprises a continuous-time loop filter.

20 . The circuit of claim 18 , further comprising a second FIR digital to analog converter coupled between an output of the 1-bit or 1.5-bit digital delta-sigma modulator and the input of the analog loop filter.

Assignees

• Infineon Technologies Ag

Inventors

• Ortmanns Maurits
• Kauffman John G
• Abdelaal Ahmed

Classifications

• H03M3/344

  by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing · CPC title

• H03M3/424

  the quantiser being a multiple bit one · CPC title

• H03M3/452

  with weighted feedforward summation, i.e. with feedforward paths from more than one filter stage to the quantiser input · CPC title

• H03M3/454

  with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage · CPC title

• H03M3/414

  having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type · CPC title