Power amplifier system

Patent metadata

Field	Value
Publication number	US-12489408-B2
Application number	US-202217972795-A
Country	US
Kind code	B2
Filing date	Oct 25, 2022
Priority date	Nov 19, 2021
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

A power amplifier system is disclosed having an N number of transistors coupled together drain-to-source between a supply node and a fixed voltage node, wherein a first one of the N number of transistors coupled nearest to the fixed voltage node is configured to operate as an amplifying device in an ON-mode, and remaining ones of the N number of transistors are configured to operate as cascode devices in the ON-mode and to operate as turned-off switches in an OFF-mode. A controller is configured to place the N number of transistors in the first mode when a radio frequency (RF) signal is to be amplified by the first one of the N number of transistors and to place the N number of transistors in the second mode when the RF signal is not to be amplified by the first one of the N number of transistors.

First claim

What is claimed is:

1 . A power amplifier system comprising:
an N number of transistors coupled together drain-to-source between a supply node and a fixed voltage node with N being a counting number, wherein a first one of the N number of transistors coupled nearest to the fixed voltage node is configured to selectively operate as an amplifying device in an ON-mode, and remaining ones of the N number of transistors are configured to selectively operate as cascode devices in the ON-mode and to selectively operate as turned-off switches in an OFF-mode; and a controller configured to place the N number of transistors in the ON-mode when a radio frequency (RF) signal is to be amplified by the first one of the N number of transistors and to place the N number of transistors in the OFF-mode when the RF signal is not to be amplified by the first one of the N number of transistors, wherein the controller is further configured to provide switch control voltage levels through a serial switch output terminal selectively coupled to the gates of the remaining ones of the N number of transistors that are configured to selectively operate as cascode devices in the ON-mode and to selectively operate as turned-off switches in the OFF-mode.

2 . The power amplifier system of claim 1 , further comprising an N+1 transistor coupled between the N number of transistors and the supply node, wherein the N+1 transistor is configured to selectively operate as an amplifying device in the ON-mode, and the controller is further configured to place the N+1 transistor in the ON-mode when the RF signal is to be amplified by both the first one of the N number of transistors and the N+1 transistor.

3 . The power amplifier system of claim 2 wherein substantially one-half of the N+1 transistors are P-channel field-effect transistors (FETs) and a remainder of the N+1 transistors are N-channel FETs.

4 . The power amplifier system of claim 1 , wherein the first one of the N number of transistors is configured to be a turned-on switch when the remaining N number of transistors are in the OFF-mode and the controller is further configured to place the first one of the N number of transistors in a conductive state to provide a current path to the fixed voltage node for the remaining N number of transistors in the OFF-mode.

5 . The power amplifier system of claim 1 wherein the controller is further configured to provide switch control voltage levels through a parallel switch output terminal selectively coupled to the gate of the first one of the N number of transistors coupled nearest to the fixed voltage node that is configured to selectively operate as an amplifying device in the ON-mode and a parallel switch in the OFF-mode.

6 . The power amplifier system of claim 1 further comprising an N number of gate resistors, each of which is coupled to a gate of a respective one of the N number of transistors selectively coupled through an N number of switches to an ON/OFF voltage output terminal.

7 . The power amplifier system of claim 6 wherein the controller is configured to open and close the N number of switches by way of a control bus.

8 . The power amplifier system of claim 7 further comprising a plurality of series-coupled gate resistors coupled between the gates of the N number of transistors.

9 . The power amplifier system of claim 1 wherein the N number of transistors is of the partially depleted silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) type.

10 . The power amplifier system of claim 1 wherein the N number of transistors is of the fully depleted silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) type.

11 . The power amplifier system of claim 1 further comprising bias circuitry that is coupled to the gates of the N number of transistors and is configured to bias the N number of transistors for amplifier operation.

12 . The power amplifier system of claim 11 further including switches coupled between the bias circuitry and gates of the N number of transistors, wherein the controller is configured to close the switches to provide bias in the ON-mode and open the switches in the OFF-mode.

13 . The power amplifier of claim 1 wherein the fixed voltage node is ground.

14 . A method of operating a power amplifier system comprising an N number of transistors coupled together drain-to-source between a supply node and a fixed voltage node with N being a counting number, wherein a first one of the N number of transistors coupled nearest to the fixed voltage node, and a controller configured to control switches coupled between gates of the N number of transistors and a serial switch output terminal, the method comprising:
selectively closing the switches by way of the controller to place the N number of transistors in the OFF-mode when an RF signal is not to be amplified by the first one of the N number of transistors; selectively opening the switches by way of the controller to place the N number of transistors in the ON-mode when the RF signal is to be amplified by the first one of the N number of transistors; and providing switch control voltage levels by way of the controller through the serial switch output terminal coupled to the gates of remaining ones of the N number of transistors, wherein the remaining ones are selectively operated as cascode devices in the ON-mode and as turned-off switches in the OFF-mode.

15 . A wireless communication device comprising:
a baseband processor; transmit circuitry configured to receive encoded data from the baseband processor and to modulate a carrier signal with the encoded data, wherein the transmit circuitry comprises:
an N number of transistors coupled together drain-to-source between a supply node and a fixed voltage node with N being a counting number, wherein a first one of the N number of transistors coupled nearest to the fixed voltage node is configured to selectively operate as an amplifying device in an ON-mode, and remaining ones of the N number of transistors are configured to selectively operate as cascode devices in the ON-mode and to selectively operate as turned-off switches in an OFF-mode; and
a controller configured to place the N number of transistors in the ON-mode when a radio frequency (RF) signal is to be amplified by the first one of the N number of transistors and to place the N number of transistors in the OFF-mode when the RF signal is not to be amplified by the first one of the N number of transistors, wherein the controller is further configured to provide switch control voltage levels through a serial switch output terminal selectively coupled to the gates of the remaining ones of the N number of transistors that are configured to selectively operate as cascode devices in the ON-mode and to selectively operate as turned-off switches in the OFF-mode; and
at least one antenna coupled to the transmit circuitry to transmit the carrier signal.

16 . The wireless communication device of claim 15 further comprising an N+1 transistor coupled between the N number of transistors and the supply node, wherein the N+1 transistor is configured to selectively operate as an amplifying device in the ON-mode, and the controller is further configured to place the N+1 transistor in the ON-mode when the RF signal is to be amplified by both the first one of the N number of transistors and the N+1 transistor.

17 . The wireless communication device of claim 16 wherein substantially one-half of the N+1 transistors are P-channel field-effect transistors (FETs) and a remainder of the N+1 tran

Assignees

• Qorvo Us Inc

Inventors

• Scott Baker
• Maxim George
• Woo Chong

Classifications

• H03F3/245

  with semiconductor devices only · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F2203/30084

  the pull circuit of the SEPP amplifier being a cascode circuit · CPC title

• H03F2203/30117

  the push circuit of the SEPP amplifier being a cascode circuit · CPC title

• H03F3/195 Primary

  in integrated circuits · CPC title