Method for manufacturing semiconductor device
US-2020176271-A1 · Jun 4, 2020 · US
Semiconductor device and method of disposing electrical components above and below substrate
US12489078B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12489078-B2 |
| Application number | US-202217656508-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 25, 2022 |
| Priority date | Mar 30, 2021 |
| Publication date | Dec 2, 2025 |
| Grant date | Dec 2, 2025 |
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- Title
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- Abstract
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- First independent claim
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Abstract
Official abstract text for this publication.
A semiconductor device has a substrate with a die mounting site and a plurality of leads. A first electrical component is disposed over a first surface of the die mounting site. A second electrical component is disposed over a second surface of the die mounting site opposite the first surface of the die mounting site. A first bond wire is coupled between the first electrical component and a first lead, and a second bond wire is coupled between the second electrical component and a second lead. A first encapsulant is deposited over the first electrical component, and a second encapsulant is deposited over the second electrical component with the leads exposed between the first encapsulant and second encapsulant. The leads are exposed from the first encapsulant and second encapsulant on a side of the semiconductor device.
First claim
Opening claim text (preview).
What is claimed: 1 . A semiconductor device, comprising: a substrate including a die mounting site and a plurality of leads; a first electrical component disposed over a first surface of the die mounting site; a second electrical component disposed over a second surface of the die mounting site opposite the first surface of the die mounting site; and an encapsulant deposited over the first electrical component and the second electrical component with a channel formed in all sides of the encapsulant proximate to the second electrical component and completely around the second electrical component and extending to a center location of the substrate and further extending partially but not completely through the plurality of leads to form a notch in the plurality of leads at the center location of the substrate while leaving the encapsulant proximate to the first electrical component to be wider than the encapsulant proximate to the second electrical component. 2 . The semiconductor device of claim 1 , further including: a first bond wire coupled between the first electrical component and a first lead of the plurality of leads; and a second bond wire coupled between the second electrical component and a second lead of the plurality of leads. 3 . The semiconductor device of claim 1 , wherein the encapsulant includes: a first encapsulant deposited over the first electrical component; and a second encapsulant deposited over the second electrical component with the leads exposed between the first encapsulant and second encapsulant. 4 . The semiconductor device of claim 3 , wherein the leads are exposed from the first encapsulant and second encapsulant on a side of the semiconductor device. 5 . The semiconductor device of claim 3 , wherein an area of a surface of the first encapsulant is greater than an area of a surface of the second encapsulant opposite the surface of the first encapsulant. 6 . A semiconductor device, comprising: a substrate including a die mounting site and a plurality of leads; a first electrical component disposed over a first surface of the die mounting site; a second electrical component disposed over a second surface of the die mounting site opposite the first surface of the die mounting site; and an encapsulant deposited over the first electrical component and the second electrical component with an area of a first surface of the encapsulant proximate to the first electrical component being greater than an area of a second surface of the encapsulant proximate to the second electrical component and opposite the first surface of the encapsulant and a notch formed in the plurality of leads at a center location of the substrate. 7 . The semiconductor device of claim 6 , further including: a first bond wire coupled between the first electrical component and a first lead on the substrate; and a second bond wire coupled between the second electrical component and a second lead on the substrate. 8 . The semiconductor device of claim 7 , further including a third electrical component disposed over the first lead and second lead on the substrate. 9 . The semiconductor device of claim 7 , further including a metal layer formed over the first lead on the substrate. 10 . The semiconductor device of claim 7 , wherein the encapsulant includes: a first encapsulant deposited over the first electrical component; and a second encapsulant deposited over the second electrical component. 11 . The semiconductor device of claim 10 , wherein an area of a surface of the first encapsulant is greater than an area of a surface of the second encapsulant opposite the surface of the first encapsulant. 12 . The semiconductor device of claim 6 , further including a printed circuit board, wherein the semiconductor device is disposed in an opening through the printed circuit board with the encapsulant proximate to the second electrical component disposed through the opening to extend beyond a first surface of the printed circuit board as the area of the second surface of the encapsulant is less than an area of the opening while the encapsulant proximate to the first electrical component remains above a second surface of the printed circuit board opposite the first surface of the printed circuit board as the area of the first surface of the encapsulant is greater than the area of the opening. 13 . The semiconductor device of claim 6 , wherein a first surface area of the encapsulant proximate to the first electrical component is wider than a second surface area of the encapsulant proximate to the second electrical component opposite the first surface area of the encapsulant. 14 . A semiconductor device, comprising: a substrate including a die mounting site and a plurality of leads; a first electrical component disposed over a first surface of the die mounting site; a second electrical component disposed over a second surface of the die mounting site opposite the first electrical component; and an encapsulant deposited over the first electrical component and the second electrical component with the encapsulant proximate to the first electrical component being wider than the encapsulant proximate to the second electrical component and a notch formed in the plurality of leads proximate to a center location of the substrate. 15 . The semiconductor device of claim 14 , further including: a first bond wire coupled between the first electrical component and a first lead on the substrate; and a second bond wire coupled between the second electrical component and a second lead on the substrate. 16 . The semiconductor device of claim 15 , further including a third electrical component disposed over the first lead and second lead on the substrate. 17 . The semiconductor device of claim 15 , further including a metal layer formed over the first lead on the substrate. 18 . The semiconductor device of claim 14 , wherein an area of a surface of the encapsulant deposited over the first electrical component is greater than an area of a surface of the encapsulant deposited over the second electrical component. 19 . The semiconductor device of claim 14 , further including a printed circuit board, wherein the semiconductor device is disposed in an opening through the printed circuit board with the encapsulant proximate to the second electrical component disposed through the opening to extend beyond a first surface of the printed circuit board while the encapsulant proximate to the first electrical component remains above a second surface of the printed circuit board opposite the first surface of the printed circuit board. 20 . The semiconductor device of claim 14 , wherein a first surface area of the encapsulant proximate to the first electrical component is wider than a second surface area of the encapsulant proximate to the second electrical component opposite the first surface area of the encapsulant.
Assignees
Inventors
Classifications
between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title
Package configurations · CPC title
the semiconductor body being completely enclosed · CPC title
batch processes · CPC title
of bond wires · CPC title
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Frequently asked questions
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- What does patent US12489078B2 cover?
- A semiconductor device has a substrate with a die mounting site and a plurality of leads. A first electrical component is disposed over a first surface of the die mounting site. A second electrical component is disposed over a second surface of the die mounting site opposite the first surface of the die mounting site. A first bond wire is coupled between the first electrical component and a fir…
- Who is the assignee on this patent?
- Utac Headquarters Pte Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W90/811. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Dec 02 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).