Gate driver

Patent metadata

Field	Value
Publication number	US-12488766-B2
Application number	US-202418675139-A
Country	US
Kind code	B2
Filing date	May 28, 2024
Priority date	Sep 26, 2023
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

A gate driver includes a plurality of stages. At least one of the stages includes a control circuit configured to control a first control node in response to a first carry clock signal, a node separation transistor connected between the first control node and a second control node, a carry output circuit configured to output a carry signal in response to a voltage of the second control node, and a plurality of gate output circuits configured to output a plurality of gate signals having different timings in response to the voltage of the second control node.

First claim

What is claimed is:

1 . A gate driver comprising a plurality of stages, wherein at least one of the stages includes:
a control circuit configured to control a first control node in response to a first carry clock signal; a node separation transistor connected between the first control node and a second control node; a carry output circuit configured to output a carry signal in response to a voltage of the second control node; and a plurality of gate output circuits configured to output a plurality of gate signals having different timings in response to the voltage of the second control node.

2 . The gate driver of claim 1 , wherein the node separation transistor separates the first control node and the second control node to control a voltage of the first control node.

3 . The gate driver of claim 1 , wherein the node separation transistor includes a gate electrode configured to receive a high gate voltage, a first electrode connected to the first control node, and a second electrode connected to the second control node.

4 . The gate driver of claim 1 , wherein the control circuit includes:
an input circuit configured to provide an input signal to the first control node in response to the first carry clock signal; a first selection circuit configured to provide a first selection signal to a first inversion control node in response to the first selection signal; and a first inversion control circuit configured to control a voltage of the first inversion control node based on a voltage of the first control node.

5 . The gate driver of claim 4 , wherein the input circuit includes a first transistor including a gate electrode configured to receive the first carry clock signal, a first electrode configured to receive the input signal, and a second electrode connected to the first control node,
wherein the first selection circuit includes a fourth transistor including a gate electrode configured to receive the first selection signal, a first electrode configured to receive the first selection signal, and a second electrode, a fifth transistor including a gate electrode connected to the second electrode of the fourth transistor, a first electrode configured to receive the first selection signal, and a second electrode connected to the first inversion control node, a sixth transistor including a gate electrode connected to the first control node, a first electrode configured to receive a first low gate voltage, and a second electrode connected to the gate electrode of the fifth transistor, and a first capacitor including a first electrode connected to the gate electrode of the fifth transistor and a second electrode connected to the first inversion control node, and wherein the first inversion control circuit includes a seventh transistor including a gate electrode connected to the first control node, a first electrode configured to receive a second low gate voltage, and a second electrode connected to the first inversion control node.

6 . The gate driver of claim 4 , wherein the control circuit further includes:
a second selection circuit configured to provide a second selection signal to a second inversion control node in response to the second selection signal; and a second inversion control circuit configured to control a voltage of the second inversion control node based on the voltage of the first control node.

7 . The gate driver of claim 6 , wherein the second selection circuit includes:
an eighth transistor including a gate electrode configured to receive the second selection signal, a first electrode configured to receive the second selection signal, and a second electrode; a ninth transistor including a gate electrode connected to the second electrode of the eighth transistor, a first electrode configured to receive the second selection signal, and a second electrode connected to the second inversion control node; a tenth transistor including a gate electrode connected to the first control node, a first electrode configured to receive a first low gate voltage, and a second electrode connected to the gate electrode of the ninth transistor; and a second capacitor including a first electrode connected to the gate electrode of the ninth transistor and a second electrode connected to the second inversion control node, and wherein the second inversion control circuit includes an 11th transistor including a gate electrode connected to the first control node, a first electrode configured to receive a second low gate voltage, and a second electrode connected to the second inversion control node.

8 . The gate driver of claim 4 , wherein the control circuit further includes:
a second transistor including a gate electrode configured to receive a reset signal, a first electrode configured to receive a first low gate voltage, and a second electrode connected to the first control node; and a third transistor including a gate electrode connected to the first control node, a first electrode configured to receive a high gate voltage, and a second electrode.

9 . The gate driver of claim 1 , wherein the carry output circuit includes:
a 15th transistor including a gate electrode connected to the second control node, a first electrode configured to receive a second carry clock signal, and a second electrode connected to a carry output node through which the carry signal is output; a 16th transistor including a gate electrode connected to a first inversion control node, a first electrode configured to receive a second low gate voltage, and a second electrode connected to the carry output node; a 12th transistor including a gate electrode configured to receive the second carry clock signal, a first electrode connected to the first control node, and a second electrode; a 13th transistor including a gate electrode connected to the first inversion control node, a first electrode connected to the second electrode of the 12th transistor, and a second electrode connected to the carry output node; and a third capacitor including a gate electrode connected to the second control node and a second electrode connected to the carry output node.

10 . The gate driver of claim 9 , wherein the carry output circuit further includes:
a 17th transistor including a gate electrode connected to the second inversion control node, a first electrode configured to receive the second low gate voltage, and a second electrode connected to the carry output node; and a 14th transistor including a gate electrode connected to the second inversion control node, a first electrode connected to the second electrode of the 12th transistor, and a second electrode connected to the carry output node.

11 . The gate driver of claim 1 , wherein the gate output circuits include a first gate output circuit configured to output a first gate signal in response to the voltage of the second control node, a second gate output circuit configured to output a second gate signal in response to the voltage of the second control node, a third gate output circuit configured to output a third gate signal in response to the voltage of the second control node, and a fourth gate output circuit configured to output a fourth gate signal in response to the voltage of the second control node,
wherein the first gate output circuit includes: a 18Ath transistor including a gate electrode connected to the second control node, a first electrode configured to receive a second clock signal, and a second electrode connected to a first gate output node through which the first gate signal is output; and a 19Ath transistor including a gate electrode connected to a first inversion control node, a first electrode configured to receive a first

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Minjoo
• Byun Minwoo
• Oh Kyonghwan
• Choi Yang-Hwa
• Jeon Donghwan

Classifications

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• H03K3/012

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title