Display substrate reducing arrangement space occupied by second electrostatic discharge circuit

Patent metadata

Field	Value
Publication number	US-12488760-B2
Application number	US-202318689083-A
Country	US
Kind code	B2
Filing date	Aug 8, 2023
Priority date	Aug 30, 2022
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

The present disclosure provides a display substrate including a base substrate, a plurality of data lines, a plurality of multiplexing circuits, a plurality of multiplexing data lines, a plurality of first electrostatic discharge circuits, a plurality of second electrostatic discharge circuits, and a plurality of first signal lines located on the base substrate. The plurality of multiplexing circuits are sequentially arranged along edges of the display region. The plurality of multiplexing circuits are electrically connected with the plurality of multiplexing data lines and the plurality of data lines. The plurality of first electrostatic discharge circuits are electrically connected to the plurality of multiplexing data lines, and the plurality of second electrostatic discharge circuits are electrically connected to the plurality of first signal lines.

First claim

The invention claimed is:

1 . A display substrate, comprising a display region and a bezel region located around the display region, the display substrate comprising:
a base substrate; a plurality of data lines located on the base substrate, located in the display region, wherein the plurality of data lines are configured to provide data signals to pixels of the display region; a plurality of multiplexing circuits, a plurality of multiplexing data lines, a plurality of first electrostatic discharge circuits, a plurality of second electrostatic discharge circuits, and a plurality of first signal lines located in the bezel region; wherein the plurality of multiplexing circuits are sequentially arranged along edges of the display region, the plurality of multiplexing circuits are electrically connected with the plurality of multiplexing data lines and the plurality of data lines, the plurality of first electrostatic discharge circuits are electrically connected with the plurality of multiplexing data lines, and the plurality of second electrostatic discharge circuits are electrically connected with the plurality of first signal lines; the plurality of first electrostatic discharge circuits and the plurality of second electrostatic discharge circuits are located at a side of the plurality of multiplexing circuits away from the display region, and the plurality of second electrostatic discharge circuits are interspersed in the plurality of first electrostatic discharge circuits, wherein the bezel region comprises a first bezel region located at a side of the display region in a second direction, and the plurality of multiplexing circuits are located in the first bezel region and arranged side by side along a first direction, and the first direction intersects with the second direction, wherein the display substrate further comprises a first power supply line located in the bezel region, and the first power supply line at least comprises a first sub-power supply line, a second sub-power supply line and a third sub-power supply line located in the first bezel region; the first sub-power supply line, the second sub-power supply line and the third sub-power supply line all extend along the second direction; the plurality of multiplexing circuits are separated by the second sub-power supply lines in the first direction.

2 . The display substrate according to claim 1 , wherein at least one of the plurality of second electrostatic discharge circuits is located at a side of the plurality of first electrostatic discharge circuits away from the display region.

3 . The display substrate according to claim 1 , wherein the plurality of multiplexing circuits are electrically connected to the plurality of data lines in the display region through a plurality of data fan-out lines, and the plurality of data fan-out lines are of same layer structure.

4 . The display substrate according to claim 1 , wherein the display substrate has a first centerline parallel to the second direction, the plurality of second electrostatic discharge circuits are located in a region, close to the first centerline, within the first bezel region and an edge region, away from the first centerline, within the first bezel region.

5 . The display substrate according to claim 4 , wherein the plurality of first signal lines comprises a plurality of multiplexing control lines and a plurality of drive signal lines.

6 . The display substrate according to claim 5 , wherein the plurality of second electrostatic discharge circuits located at edges of the first bezel region away from the first centerline is electrically connected to the plurality of drive signal lines respectively to discharge static electricity of the plurality of drive signal lines.

7 . The display substrate according to claim 1 , wherein the bezel region further comprises a second bezel region located at a side of the display region away from the first bezel region along the second direction;
the display substrate further comprises a plurality of test circuits located in the second bezel region, and the plurality of test circuits are arranged side by side along the first direction.

8 . The display substrate according to claim 7 , wherein the bezel region further comprises a third bezel region and a fourth bezel region located at opposite sides of the display region along the first direction, a first corner region connecting the first bezel region and the third bezel region, a second corner region connecting the third bezel region and the second bezel region, a third corner region connecting the second bezel region and the fourth bezel region, and a fourth corner region connecting the fourth bezel region and the first bezel region,
the display substrate further comprises a gate drive circuit located in the third bezel region, the fourth bezel region, the first corner region, the second corner region, the third corner region and the fourth corner region.

9 . The display substrate according to claim 8 , wherein the plurality of multiplexing circuits close to the first corner region and the fourth corner region are electrically connected to the plurality of data lines of the display region through arc-shaped data fan-out lines.

10 . The display substrate according to claim 8 , wherein a test circuit close to the second corner region and the third corner region is electrically connected to the plurality of data lines of the display region through arc-shaped data connection lines.

11 . The display substrate according to claim 8 , wherein the plurality of multiplexing circuits are not provided in the first corner region and the fourth corner region, and the plurality of multiplexing circuits are all provided in the first bezel region.

12 . The display substrate according to claim 1 , wherein the first power supply line further comprises a fourth sub-power supply line and a fifth sub-power supply line located in the first bezel region; the fourth sub-power supply line and the fifth sub-power supply line both extend along the first direction, and the fourth sub-power supply line is located at a side of the fifth sub-power supply line close to the display region; the fourth sub-power supply line and the fifth sub-power supply line are both electrically connected to the first sub-power supply line, the second sub-power supply line and the third sub-power supply line; the plurality of multiplexing circuits, the plurality of first electrostatic discharge circuits and the plurality of second electrostatic discharge circuits are located between the fourth sub-power supply line and the fifth sub-power supply line.

13 . The display substrate according to claim 12 , wherein at least one of the plurality of multiplexing data lines is electrically connected to a compensation resistor located at a side of the first electrostatic discharge circuit away from the display region;
the first bezel region at least comprises a peripheral circuit region, a signal access region located at a side of the peripheral circuit region away from the display region, and an encapsulation region located between the peripheral circuit region and the signal access region, wherein the compensation resistor is located in the encapsulation region and serves as an encapsulation underlay substrate.

14 . The display substrate according to claim 13 , wherein a portion of the fifth sub-power supply line located within the encapsulation region, and a portion of the second power supply line located within the encapsulation region serve as a first encapsulation adhesive underlay substrate, and a plurality of openings are provided on the first encapsulation

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Lu Yanwei
• Yan Zhuoran
• Shi Quan
• Cheng Yudiao
• Ji Fengli

Classifications

• G09G2330/04

  Display protection · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title