Display panel and display device

Patent metadata

Field	Value
Publication number	US-12488753-B2
Application number	US-202418759707-A
Country	US
Kind code	B2
Filing date	Jun 28, 2024
Priority date	Jun 30, 2023
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

A display panel and a display device are provided. A compensation module of a pixel circuit of a display panel is on in a bias adjustment stage, a data write stage, and a time period between the bias adjustment stage and the data write stage; and/or, a reset module of the pixel circuit is on in the bias adjustment stage and a reset stage and is turned off at least after the compensation module is turned on.

First claim

What is claimed is:

1 . A display panel, comprising:
a pixel circuit and a light-emitting element; wherein the pixel circuit comprises a drive module, a compensation module, a reset module, a data write module, and a bias adjustment module; the drive module comprises a drive transistor; the drive transistor comprises a gate, a first electrode, and a second electrode; and the compensation module is connected between the gate of the drive transistor and the second electrode of the drive transistor; a working process of the display panel comprises a reset stage, a data write stage, and a bias adjustment stage; the reset module is configured to supply a reset signal to the drive transistor in the reset stage; the data write module is configured to supply a data signal to the drive transistor in the data write stage; and in the bias adjustment stage, the bias adjustment module is turned on and is configured to supply a bias adjustment signal to the drive transistor; wherein the display panel satisfies at least one of the following: the compensation module is on in the bias adjustment stage, the data write stage, and a time period between the bias adjustment stage and the data write stage; or the reset module is on in the bias adjustment stage and the reset stage and is turned off at least after the compensation module is turned on, and a time period in which the reset module is turned on overlaps a time period in which the compensation module is turned on.

2 . The display panel according to claim 1 , wherein
the compensation module is on in the bias adjustment stage, the data write stage, and the time period between the bias adjustment stage and the data write stage; and a time length of the bias adjustment stage is Ws, a time length of the data write stage is Wd, and a time length of the time period in which the compensation module is turned on is Wc, wherein the bias adjustment stage is located before the data write stage, a time length of a time period between an end of the bias adjustment stage and a start of the data write stage is Wt 1 , and Wc≥(Ws+Wd+Wt 1 ); or the bias adjustment stage is located after the data write stage, a time length of a time period between an end of the data write stage and a start of the bias adjustment stage is Wt 2 , and Wc≥(Ws+Wd+Wt 2 ).

3 . The display panel according to claim 2 , wherein
the reset stage is located between the bias adjustment stage and the data write stage, and the compensation module is on in the reset stage.

4 . The display panel according to claim 3 , wherein
a time length of the time period in which the reset module is turned on is Wr; and the bias adjustment stage is located before the data write stage, and the time length of the time period between the end of the bias adjustment stage and the start of the data write stage is Wt 1 ; wherein Wr<Wt 1 .

5 . The display panel according to claim 2 , wherein
the bias adjustment stage is located before the data write stage; and a time length of a time period between turning-on of the compensation module and the start of the bias adjustment stage is Wb 1 , and a time length of a time period between the end of the data write stage and turning-off of the compensation module is Wa 1 ; wherein Wb 1 ≥0, and/or Wa 1 ≥0.

6 . The display panel according to claim 5 , wherein
Wb 1≠ Wa 1.

7 . The display panel according to claim 6 , wherein
Wb 1< Wa 1.

8 . The display panel according to claim 2 , wherein
the bias adjustment stage is located after the data write stage; and a time length of a time period between turning-on of the compensation module and the start of the data write stage is Wb 2 , and a time length of a time period between the end of the bias adjustment stage and turning-off of the compensation module is Wa 2 ; wherein Wb 2 ≥0, and/or Wa 2 ≥0.

9 . The display panel according to claim 8 , wherein
Wb 2≠ Wa 2.

10 . The display panel according to claim 9 , wherein
Wb 2> Wa 2.

11 . The display panel according to claim 1 , wherein
the reset module is on in the bias adjustment stage and the reset stage and is turned off at least after the compensation module is turned on; and a time length of the bias adjustment stage is Ws, a time length of a time period between an end of the bias adjustment stage and turning-on of the compensation module is Wt 3 , and a time length of the reset stage is Wr; wherein Wr≥(Ws+Wt 3 ).

12 . The display panel according to claim 11 , wherein
a time length of a time period when the reset stage overlaps the time period when the compensation module is turned on is Wt 4 ; wherein Wr≥(Ws+Wt 3 +Wt 4 ).

13 . The display panel according to claim 12 , wherein
a time length of a time period between a start of the reset stage and a start of the bias adjustment stage is Wb 3 ; wherein Wb 3 ≥0.

14 . The display panel according to claim 13 , wherein
Wb 3≠ Wt 4.

15 . The display panel according to claim 13 , wherein
Wb 3≤ Wt 4.

16 . The display panel according to claim 1 , wherein
the reset module is connected to the gate of the drive transistor; the data write module is connected to the first electrode of the drive transistor; and the bias adjustment module is connected to the first electrode of the drive transistor or the second electrode of the drive transistor.

17 . The display panel according to claim 1 , wherein
when the compensation module is turned on, the bias adjustment module transmits the bias adjustment signal to the gate of the drive transistor in the bias adjustment stage; and when the compensation module is turned off, the bias adjustment module transmits the bias adjustment signal to the first electrode of the drive transistor and/or the second electrode of the drive transistor in the bias adjustment stage.

18 . The display panel according to claim 1 , wherein
the bias adjustment stage comprises a first bias adjustment stage and a second bias adjustment stage, the first bias adjustment stage is located before the data write stage, and the second bias adjustment stage is located after the data write stage, wherein the compensation module is on in the first bias adjustment stage, the data write stage, and a time period between the first bias adjustment stage and the data write stage.

19 . The display panel according to claim 1 , wherein
the bias adjustment stage comprises a first bias adjustment stage and a second bias adjustment stage, the first bias adjustment stage is located before the data write stage, and the second bias adjustment stage is located after the data write stage, wherein the reset module is on in the first bias adjustment stage and the reset stage and is turned off at least after the compensation module is turned on.

20 . A display device, comprising a display panel, wherein the display panel comprising: a pixel circuit and a light-emitting element;
wherein the pixel circuit comprises a drive module, a compensation module, a reset module, a data write module, and a bias adjustment module; the drive module comprises a drive transistor; the drive transistor comprises a gate, a first electrode, and a second electrode; and the compensation module is connected between the gate of the drive transistor and the second electrode of the drive transistor; a working process of the display panel comprises a reset stage, a data write stage, and a bias adjustment stage; the reset module is configured to supply a reset signal to the drive tr

Assignees

• Xiamen Tianma Display Tech Co Ltd

Inventors

• Lai Qingjun
• Yang Jinjin

Classifications

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title