Array substrate and display apparatus

Patent metadata

Field	Value
Publication number	US-12488746-B2
Application number	US-202318292531-A
Country	US
Kind code	B2
Filing date	Feb 24, 2023
Priority date	Feb 24, 2023
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

An array substrate is provided. The array substrate includes pixels arranged in a plurality of repeating units. The array substrate includes a plurality of source electrode connecting lines and a plurality of data connecting pads in the repeating unit, and a plurality of data lines. A respective source electrode connecting line of the plurality of source electrode connecting lines connects first electrodes of a first transistor and a second transistor in a respective pixel driving circuit together. The respective source electrode connecting line is further connected to a respective data connecting pad of the plurality of data connecting pads. The respective data connecting pad is connected to a respective data line of the plurality of data lines. A maximum width of the respective source electrode connecting line is greater than at least 75% of a maximum width of a respective anode.

First claim

What is claimed is:

1 . An array substrate, comprising pixels arranged in a plurality of repeating units;
wherein a respective repeating unit of the plurality of repeating units comprises a plurality of pixels, a respective pixel comprising one or more subpixels; wherein the array substrate comprises a plurality of source electrode connecting lines and a plurality of data connecting pads in the repeating unit, and a plurality of data lines; a respective source electrode connecting line of the plurality of source electrode connecting lines connects first electrodes of a first transistor and a second transistor in a respective pixel driving circuit together; the respective source electrode connecting line is further connected to a respective data connecting pad of the plurality of data connecting pads; and the respective data connecting pad is connected to a respective data line of the plurality of data lines; wherein the array substrate further comprises a plurality of anodes; a respective anode of the plurality of anodes has a first maximum width; and the respective source electrode connecting line has a second maximum width; the second maximum width is greater than at least 75% of the first maximum width.

2 . The array substrate of claim 1 , wherein, in the repeating unit, a number of pixel driving circuits is N, N being an integer equal to or greater than 1;
a number of data lines configured to provide data signals to the repeating unit is (N/2); a number of data connecting pads in the repeating unit is (N/2); and a number of source electrode connecting lines in the repeating unit is (N/2).

3 . The array substrate of claim 1 , wherein, in the repeating unit, first electrodes of four transistors respectively in two pixel driving circuits respectively in two adjacent pixels in the same column are connected to a same source electrode connecting line; and
wherein the four transistor comprises a first transistor and a second transistor in a first pixel driving circuit in a first adjacent pixel in the same column, and a first transistor and a second transistor in a second pixel driving circuit in a second adjacent pixel in the same column.

4 . The array substrate of claim 1 , wherein the array substrate further comprises a plurality of drain electrode connecting lines in the repeating unit; and
a respective drain electrode connecting line of the plurality of drain electrode connecting lines connects second electrodes of the first transistor and the second transistor in the respective pixel driving circuit together.

5 . The array substrate of claim 4 , wherein the array substrate further comprises a plurality of first node connecting lines in the repeating unit;
the respective drain electrode connecting line is connected to a respective first node connecting line of the plurality of first node connecting lines; and the respective first node connecting line is electrically connected to a gate electrode of a driving transistor in the respective pixel driving circuit.

6 . The array substrate of claim 5 , wherein, in the repeating unit, a number of transistors having second electrodes connected to a first node in the repeating unit is 2N;
a number of drain electrode connecting lines in the repeating unit is N; and a number of first node connecting lines in the repeating unit is N.

7 . The array substrate of claim 5 , wherein the array substrate further comprises a plurality of first connecting pads, a plurality of first connecting pads, and a plurality of first capacitor electrodes in the repeating unit;
the respective first node connecting line is connected to a respective first connecting pad of the plurality of first connecting pads; and a respective first connecting pad of the plurality of first connecting pads is connected to a respective first capacitor electrode of the plurality of first capacitor electrodes.

8 . The array substrate of claim 1 , wherein the array substrate further comprises a plurality of second node connecting lines, a plurality of second connecting pads, and a plurality of anode connecting pads in the repeating unit;
a respective second node connecting line of the plurality of second node connecting lines is connected to a second electrode of a driving transistor in the respective pixel driving circuit; the respective second node connecting line is connected to a respective second connecting pad of the plurality of second connecting pads; the respective second connecting pad is connected to a respective anode connecting pad of a plurality of anode connecting pads; and the respective anode connecting pad is connected to an anode of a respective subpixel.

9 . The array substrate of claim 1 , further comprising a low voltage signal network configured to be provided with a low voltage signal;
wherein the low voltage signal network comprises a first interference prevention block configured to shield at least portions of active layers of the first transistor and a driving transistor from electromagnetic interference; wherein the first interference prevention block is in a same layer as the active layers of the first transistor and the driving transistor.

10 . The array substrate of claim 9 , wherein the low voltage signal network further comprises a third interference prevention block configured to shield at least portions of active layers of the first transistor and the driving transistor from electromagnetic interference;
wherein the third interference prevention block is connected to the first interference prevention block, and in a layer different from the first interference prevention block; and an orthographic projection of the third interference prevention block on a base substrate at least partially overlaps with an orthographic projection of active layers of multiple driving transistors in the repeating unit on the base substrate.

11 . The array substrate of claim 10 , wherein the low voltage signal network further comprises a ground plate connected to the third interference prevention block, and in a layer different from the first interference prevention block or the third interference prevention block;
wherein the ground plate in the repeating unit extends throughout at least 50% of the repeating unit; and an orthographic projection of the ground plate on the base substrate at least partially overlaps with an orthographic projection of the third interference prevention block in the repeating unit on the base substrate; and at least partially overlaps with an orthographic projection of the first interference prevention block in the repeating unit on the base substrate.

12 . The array substrate of claim 11 , wherein the low voltage signal network further comprises a plurality of ground lines connected to the ground plate, and in a layer different from the ground plate, the first interference prevention block, or the third interference prevention block;
wherein the plurality of ground lines are in a same layer as a plurality of data lines; and the plurality of ground lines and the plurality of data lines extend along a direction substantially parallel to a second direction.

13 . The array substrate of claim 12 , wherein the low voltage signal network further comprises a second capacitor electrode connected to the plurality of ground lines, and in a layer different from the plurality of ground lines, the ground plate, the first interference prevention block, or the third interference prevention block.

14 . The array substrate of claim 1 , further comprising an interconnected voltage supply network;
wherein the interconnected voltage supply networ

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Niu Jinfei
• Cong Ning
• Zhang Can
• Wang Can
• Zhang Jingjing
• Fan Longfei
• Xuan Minghua
• Chen Xiaochuan
• Yan Jiakui

Classifications

• G09G2330/06

  Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title