Light-emitting signal generating circuit and display device

Patent metadata

Field	Value
Publication number	US-12488741-B2
Application number	US-202418910003-A
Country	US
Kind code	B2
Filing date	Oct 9, 2024
Priority date	Dec 11, 2023
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

A light-emitting signal generating circuit includes a first transistor, having a first terminal for receiving a first light-emitting signal, a gate terminal for receiving a first clock signal, and a second terminal that generates a control signal; a second transistor that has a first terminal for receiving a first reference voltage, a gate terminal, and a second terminal for outputting a second light-emitting signal; a first capacitor having a first terminal for receiving a second clock signal, and a second terminal coupled to the second terminal of the first transistor and a gate terminal of the second transistor, wherein a low level period of the first clock signal partially overlaps with a low level period of the second clock signal, and a falling edge of the second clock signal lags behind a falling edge of the first clock signal.

First claim

What is claimed is:

1 . A light-emitting signal generating circuit, comprising:
a first transistor, comprising a first terminal for receiving a first light-emitting signal, a gate terminal for receiving a first clock signal, and a second terminal for generating a control signal; a second transistor, comprising a first terminal for receiving a first reference voltage, a gate terminal, and a second terminal for outputting a second light-emitting signal; and a first capacitor, comprising a first terminal for receiving a second clock signal and a second terminal coupled to the second terminal of the first transistor and the gate terminal of the second transistor, wherein a low level period of the first clock signal partially overlaps with a low level period of the second clock signal, a high level period of the first clock signal partially overlaps with a high level period of the second clock signal, and a falling edge of the second clock signal lags behind a falling edge of the first clock signal, wherein during a period of the second clock signal coupling with the control signal through the first capacitor, the second transistor is operated in linear region.

2 . The light-emitting signal generating circuit of claim 1 , wherein the second transistor is configured to lower a level of the second light-emitting signal.

3 . The light-emitting signal generating circuit of claim 2 , wherein when the first clock signal conducts the first transistor and the control signal starts being switched to a low level but is not at a steady-state low level yet, the control signal is pulled down through a coupling effect of the first capacitor based on the falling edge of the second clock signal.

4 . The light-emitting signal generating circuit of claim 3 , wherein when the control signal is pulled down through the coupling effect of the first capacitor based on the falling edge of the second clock signal, the second transistor is operated in linear region.

5 . The light-emitting signal generating circuit of claim 3 , wherein a delay time length by which the falling edge of the second clock signal lags behind the falling edge of the first clock signal is less than half cycle of the first clock signal or less than a data signal length.

6 . The light-emitting signal generating circuit of claim 5 , wherein the data signal length is 28 microseconds (us).

7 . The light-emitting signal generating circuit of claim 1 , further comprising:
a third transistor, comprising a first terminal for receiving the first light-emitting signal, a gate terminal for receiving a first scanning signal and a second terminal; and a fourth transistor, comprising a first terminal, a gate terminal for receiving a second scanning signal, and a second terminal for receiving a third light-emitting signal.

8 . The light-emitting signal generating circuit of claim 1 , further comprising:
a discharging module, electrically coupled to the second terminal of the second transistor, wherein the discharging module is configured to pull up the second light-emitting signal according to the falling edge of the first clock signal.

9 . The light-emitting signal generating circuit of claim 8 , wherein the discharging module further comprising:
a third transistor, comprising a gate terminal for receiving the first light-emitting signal, a first terminal for adjusting a second control signal in response to the first light-emitting signal, and a second terminal for receiving a second reference voltage.

10 . A display device, comprising:
a plurality of pixel units; a plurality of light-emitting signal generating circuits, each of the light-emitting signal generating circuits comprises: a first transistor, comprising a first terminal for receiving a previous stage light-emitting signal, a gate terminal for receiving a first clock signal, and a second terminal for generating a control signal; a second transistor, comprising a first terminal for receiving a first reference voltage, a gate terminal, and a second terminal for outputting a present stage light-emitting signal to one of the pixel units; and a first capacitor, comprising a first terminal for receiving a second clock signal and a second terminal coupled to the second terminal of the first transistor and the gate terminal of the second transistor; and a delay circuit, configured to delay the first clock signal to generate a second clock signal and transmit the second clock signal to the light-emitting signal generating circuits, wherein a low level period of the first clock signal partially overlaps with a low level period of the second clock signal, a high level period of the first clock signal partially overlaps with a high level period of the second clock signal, and a falling edge of the second clock signal lags behind a falling edge of the first clock signal, wherein during a period of the second clock signal coupling with the control signal through the first capacitor, the second transistor is operated in linear region.

11 . The display device of claim 10 , wherein the second transistor is configured to lower a level of the present stage light-emitting signal.

12 . The display device of claim 11 , wherein when the first clock signal conducts the first transistor and the control signal starts being switched to a low level but is not at a steady-state low level yet, the control signal is pulled down through a coupling effect of the first capacitor based on the falling edge of the second clock signal.

13 . The display device of claim 12 , wherein when the control signal is pulled down through the coupling effect of the first capacitor based on the falling edge of the second clock signal, the second transistor is operated in linear region.

14 . The display device of claim 12 , wherein a delay time length by which the falling edge of the second clock signal lags behind the falling edge of the first clock signal is less than half cycle of the first clock signal or less than a data signal length.

15 . The display device of claim 14 , wherein the data signal length is 28 microseconds (us).

Assignees

• Auo Corp

Inventors

• Lin Wei-Li
• Yeh Yen-Wei

Classifications

• G09G2300/0852

  being a dynamic memory with more than one capacitor · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G3/32 Primary

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title