Image data transmission device and method, electronic apparatus, medium, and display system

Patent metadata

Field	Value
Publication number	US-12488728-B2
Application number	US-202117908000-A
Country	US
Kind code	B2
Filing date	Aug 3, 2021
Priority date	Aug 3, 2021
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

The disclosure provides an image data transmission device including: receiving sub-circuit, writing control component, and reading control component. The disclosure further provides an image data transmission method, including: in response to the receiving sub-circuit being in locked state, receiving, by receiving sub-circuit, image data sent by a mainboard, and writing, according to a first frame synchronous signal, the image data received from the mainboard in each clock cycle of the first frame synchronous signal into a frame of a memory, reading, according to a second frame synchronous signal, a frame from the memory in each clock cycle of the second frame synchronous signal; sending each frame read from the memory to a display component; and in response to the receiving sub-circuit being in unlocked state, stopping writing the image data into the memory. The disclosure further provides an electronic apparatus, a computer-readable medium and a display system.

First claim

What is claimed is:

1 . An image data transmission device, comprising:
a receiving sub-circuit configured to receive image data sent by a mainboard; a writing control component configured to write, in response to the receiving sub-circuit being in a locked state, image data received by the receiving sub-circuit in each clock cycle of a first frame synchronous signal into a frame of a memory according to the first frame synchronous signal, the first frame synchronous signal being an associated clock signal, and stop, in response to the receiving sub-circuit being in an unlocked state, writing the image data to the memory; a reading control component configured to read, in response to the receiving sub-circuit being in the locked state, a frame from the memory in each clock cycle of a second frame synchronous signal according to the second frame synchronous signal, wherein a first time interval exists between writing and reading a same frame, the first time interval has a length greater than or equal to a length of the clock cycle of the first frame synchronous signal, and the second frame synchronous signal is a local clock signal; and a sending component configured to send the frame read by the reading control component to a display component, wherein the image data transmission device further comprises a selecting component, wherein the reading control component is further configured to read the frame from the memory in each clock cycle of the second frame synchronous signal and send the frame to the selecting component; the selecting component is configured to send, in response to the receiving sub-circuit being in the locked state, each frame read by the reading control component to the sending component; and send, in response to the receiving sub-circuit being in the unlocked state, a predetermined prompt frame to the sending component; and the sending component is configured to send the frame selected by the selecting component to the display component, wherein the selecting component is further configured to send, in response to the receiving sub-circuit being adjusted to the unlocked state, the prompt frame to the sending component after a second time interval, and wherein the second time interval has a length smaller than or equal to a length of the clock cycle of the second frame synchronous signal.

2 . The image data transmission device according to claim 1 , further comprising:
a phase-locked loop component configured to parse and recover the first frame synchronous signal; and adjust the receiving sub-circuit to the locked state or the unlocked state.

3 . The image data transmission device according to claim 2 , wherein
the phase-locked loop component is further configured to set a clock recovery lock signal sent to the mainboard to be at a low level in response to adjusting the receiving sub-circuit to the locked state; and set the clock recovery lock signal sent to the mainboard to be at a high level in response to adjusting the receiving sub-circuit to the unlocked state.

4 . The image data transmission device according to claim 1 , wherein
the reading control component is further configured to read, in response to the receiving sub-circuit being in the locked state, the frame from the memory in each clock cycle of the second frame synchronous signal after a first target falling edge of the first frame synchronous signal, and wherein the first target falling edge is the second falling edge following a falling edge of the clock recovery lock signal.

5 . The image data transmission device according to claim 1 , wherein
the selecting component is further configured to send, in response to the receiving sub-circuit being adjusted to the unlocked state, the prompt frame to the sending component after a second target falling edge of the second frame synchronous signal, and wherein the second target falling edge is the first falling edge following a rising edge of the clock recovery lock signal.

6 . The image data transmission device according to claim 2 , wherein
during handshake with the mainboard according to a VBO protocol, the phase-locked loop component is further configured to adjust the receiving sub-circuit to the locked state after clock data recovery is completed.

7 . The image data transmission device according to claim 2 , wherein
the phase-locked loop component is further configured to adjust the receiving sub-circuit from the locked state to the unlocked state in response to an increase or a decrease of a frequency of an associated clock signal of the mainboard.

8 . A display system, comprising:
a mainboard, an image data transmission device, and a display component, wherein the image data transmission device is the image data transmission device as claimed in claim 1 .

9 . An image data transmission method, comprising:
in response to a receiving sub-circuit being in a locked state, receiving, by the receiving sub-circuit, image data sent by a mainboard, and writing, according to a first frame synchronous signal, the image data received from the mainboard in each clock cycle of the first frame synchronous signal into a frame of a memory, the first frame synchronous signal being an associated clock signal; in response to the receiving sub-circuit being in the locked state, reading, according to a second frame synchronous signal, a frame from the memory in each clock cycle of the second frame synchronous signal, wherein a first time interval exists between writing and reading a same frame, the first time interval has a length greater than or equal to a length of the clock cycle of the first frame synchronous signal, and the second frame synchronous signal is a local clock signal; sending each frame read from the memory to a display component; and in response to the receiving sub-circuit being in an unlocked state, stopping writing the image data sent by the mainboard into the memory, wherein the method further comprises: in response to the receiving sub-circuit being in the locked state, sending each frame read from the memory to the display component; and in response to the receiving sub-circuit being in the unlocked state, sending a predetermined prompt frame to the display component, wherein in response to the receiving sub-circuit being in the unlocked state, sending a predetermined prompt frame to the display component comprises: in response to the receiving sub-circuit being adjusted to the unlocked state, sending the prompt frame to the display component after a second time interval, wherein the second time interval has a length less than or equal to a length of the clock cycle of the second frame synchronous signal.

10 . The image data transmission method according to claim 9 , wherein before writing, according to a first frame synchronous signal, the image data received from the mainboard in each clock cycle of the first frame synchronous signal into a frame of a memory, the image data transmission method further comprises:
handshaking with the mainboard according to a VBO protocol, wherein after clock data recovery is completed, the receiving sub-circuit is adjusted to the locked state, and a clock recovery lock signal sent to the mainboard is set to be at a low level.

11 . The image data transmission method according to claim 9 , wherein reading, according to a second frame synchronous signal, a frame from the memory in each clock cycle of the second frame synchronous signal comprises:
detecting a first target falling edge of the first frame synchronous signal in response to the receiving sub-circuit being adjusted to the locked state, wherein the first target falling edge is the second falling edge following a fal

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Ma Xitong
• Li Tailiang

Classifications

• G09G2370/08

  Details of image data interface between the display device controller and the data line driver circuit · CPC title

• G09G2360/128

  Frame memory using a Synchronous Dynamic RAM [SDRAM] · CPC title

• G09G5/008 Primary

  Clock recovery · CPC title

• G09G5/006

  Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04) · CPC title

• G09G5/12

  Synchronisation between the display unit and other units, e.g. other display units, video-disc players · CPC title