Offloading compute processing to an input/output (I/O) device connected over a USB type-C connector

Patent metadata

Field	Value
Publication number	US-12487962-B2
Application number	US-202217748377-A
Country	US
Kind code	B2
Filing date	May 19, 2022
Priority date	May 19, 2022
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

A USB4 host system for offloading compute processing includes a host processor and a first routing circuit communicatively coupled to the host processor via an interface adapter. The first routing circuit is to decode device capability information received via a USB Type-C communication link from a second routing circuit. The device capability information indicates the second routing circuit is configured for offload processing. A downstream tunneled path is configured between the host processor and the second routing circuit based on the device capability information. The downstream tunneled path includes the USB Type-C communication link. One or more acceleration commands and operands/data from the host processor are packetized into a first plurality of USB4 tunneled packets. The first plurality of USB4 tunneled packets is encoded for transmission to the second routing circuit via the downstream tunneled path, to initiate the offload processing of the operands/data by the second routing circuit.

First claim

What is claimed is:

1 . A Universal Serial Bus 4 (USB4) host system for offloading compute processing, the system comprising:
a host processor; and a first routing circuit communicatively coupled to the host processor via an interface adapter, wherein the first routing circuit is to:
decode device capability information, the device capability information received via a USB Type-C communication link from a second routing circuit, the device capability information indicating the second routing circuit is configured for offload processing;
configure a downstream tunneled path between the host processor and the second routing circuit based on the device capability information, the downstream tunneled path including the USB Type-C communication link;
packetize one or more acceleration commands and operands/data from the host processor into a first plurality of USB4 tunneled packets; and
encode the first plurality of USB4 tunneled packets for transmission to the second routing circuit via the downstream tunneled path, to initiate the offload processing of the operands/data by the second routing circuit.

2 . The USB4 host system of claim 1 , wherein the first routing circuit is further to:
configure an upstream tunneled path between the host processor and the second routing circuit based on the device capability information, the upstream tunneled path including the USB Type-C communication link.

3 . The USB4 host system of claim 2 , wherein the first routing circuit is further to:
decode a second plurality of USB4 tunneled packets to obtain result data associated with the offload processing, the second plurality of USB4 tunneled packets received from the second routing circuit via the upstream tunneled path; and communicate the result data to the host processor.

4 . The USB4 host system of claim 3 , wherein the result data is associated with application of the one or more acceleration commands to the operands/data during the offload processing.

5 . The USB4 host system of claim 3 , wherein the device capability information indicates the second routing circuit is configured to access acceleration processing logic configured to perform the offload processing.

6 . The USB4 host system of claim 5 , wherein the first routing circuit is further to:
configure the interface adapter to enumerate as an accelerator device to the host processor, based on the device capability information indicating the second routing circuit is configured to access the acceleration processing logic configured to perform the offload processing.

7 . The USB4 host system of claim 6 , wherein the host processor is to:
reserve bandwidth resources for the accelerator device, the bandwidth resources used for: the transmission of the first plurality of USB4 tunneled packets via the downstream tunneled path; and reception of the second plurality of USB4 tunneled packets via the upstream tunneled path.

8 . The USB4 host system of claim 1 , wherein the device capability information indicates the second routing circuit is configured to access acceleration processing logic configured to perform the offload processing, wherein the acceleration processing logic includes acceleration memory, and wherein the host processor is to:
manage access to the acceleration memory of the acceleration processing logic using the downstream tunneled path.

9 . An accelerator device for offloading compute processing, the device comprising:
a Universal Serial Bus (USB) Type-C connector; a first routing circuit communicatively coupled to the USB Type-C connector, the first routing circuit configured to:
encode device capability information for transmission via the USB Type-C connector to a second routing circuit of a host system, the device capability information indicating the first routing circuit is configured for offload processing; and
de-packetize a first plurality of USB4 tunneled packets to obtain one or more acceleration commands and operands/data originating from a host processor of the host system, the first plurality of USB4 tunneled packets received from the second routing circuit via a downstream tunneled path between the host processor and the first routing circuit, the downstream tunneled path including a USB Type-C communication link of the USB Type-C connector; and
an acceleration circuit communicatively coupled to the first routing circuit, the acceleration circuit configured to perform the offload processing using the one or more acceleration commands and operands/data to obtain result data.

10 . The accelerator device of claim 9 , wherein the first routing circuit is configured to:
encode a second plurality of USB4 tunneled packets with the result data for transmission to the second routing circuit via an upstream tunneled path.

11 . The accelerator device of claim 10 , wherein the upstream tunneled path is configured between the host processor and the first routing circuit based on configuration information received from the second routing circuit via the USB Type-C communication link.

12 . The accelerator device of claim 9 , wherein the acceleration circuit comprises acceleration processing logic and acceleration memory, wherein the acceleration processing logic is configured to perform the offload processing, and wherein the first routing device provides the host processor with access to the acceleration memory via the downstream tunneled path.

13 . A method for offloading compute processing, the method comprising:
decoding by a first routing circuit of a Universal Serial Bus 4 (USB4) host system, device capability information received via a USB Type-C communication link from a second routing circuit, and the device capability information indicating the second routing circuit is configured for offload processing; configuring a downstream tunneled path between a host processor of the USB4 host system and the second routing circuit based on the device capability information, the downstream tunneled path including the USB Type-C communication link; packetizing one or more acceleration commands and operands/data from the host processor into a first plurality of USB4 tunneled packets; and encoding the first plurality of USB4 tunneled packets for transmission to the second routing circuit via the downstream tunneled path, to initiate the offload processing of the operands/data by the second routing circuit.

14 . The method of claim 13 , further comprising:
configuring an upstream tunneled path between the host processor and the second routing circuit based on the device capability information, the upstream tunneled path including the USB Type-C communication link.

15 . The method of claim 14 , further comprising:
decoding a second plurality of USB4 tunneled packets to obtain result data associated with the offload processing, the second plurality of USB4 tunneled packets received from the second routing circuit via the upstream tunneled path; and communicating the result data to the host processor.

16 . The method of claim 15 , wherein the result data is associated with application of the one or more acceleration commands to the operands/data during the offload processing.

17 . The method of claim 15 , wherein the device capability information indicates the second routing circuit is configured to access acceleration processing logic configured to perform the offload processing.

18 . The method of claim 17 , further comprising:
configuring an interface adapter of the first routing circuit to enumerate as an accelerator device to the host

Assignees

• Intel Corp

Inventors

• Nelson Aruni
• Ismail Abdul
• Mishra Ashok

Classifications

• G06F2213/0042

  Universal serial bus [USB] · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/4295 Primary

  using an embedded synchronisation · CPC title