Two-stage cache partitioning

Patent metadata

Field	Value
Publication number	US-12487928-B2
Application number	US-202217711471-A
Country	US
Kind code	B2
Filing date	Apr 1, 2022
Priority date	Apr 1, 2022
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

Techniques and mechanisms to facilitate access to a cache based on a dual basis partition scheme. In an embodiment, a first one or more registers of a processor provide information which describes multiple set-wise partitions of a cache. A second one or more registers of the processor provides additional information which describes multiple way-wise partitions of the cache. A virtual cache is defined as that region of the cache which is both in a particular set-wise partition, and in a particular way-wise partition. In another embodiment, a cache agent of the processor performs operations, based on the set-wise partitioning and the way-wise partitioning, to determine a mapping of one address—which is provided in a memory access request, and which indicates a location in one virtual cache—to another address which indicates another location in a different virtual cache.

First claim

What is claimed is:

1 . A processor comprising:
a first one or more registers to provide first information which describes a set-wise partitioning of a cache; a second one or more registers to provide second information which describes a way-wise partitioning of the cache; and first circuitry coupled to the first one or more registers and the second one or more registers, the first circuitry to:
receive a memory access request comprising a first address; and
identify a cache line of the cache based on the first address, the set-wise
partitioning, and the way-wise partitioning;
wherein:
the first one or more registers comprise a first plurality of registers which correspond to different ones of multiple set-wise partitions, respectively;
the cache comprises multiple segments which each comprise a same total number of sets; and
for each of the first plurality of registers, the register is to provide a respective first set of bits which is to identify one or more of the multiple segments as belonging to the corresponding set-wise partition.

2 . The processor of claim 1 , wherein, for each of the first plurality of registers, the register is to further provide a respective second set of bits which is to indicate a base of the corresponding set-wise partition.

3 . The processor of claim 2 , wherein, for each of the first plurality of registers, the register is to further provide a respective third set of bits to facilitate a selection of the corresponding set-wise partition.

4 . The processor of claim 1 , wherein the first one or more registers further comprise a second plurality of registers which are each to correspond to a different respective one of the multiple set-wise partitions; and
wherein, for each register of the second plurality of registers, the register is to identify one or more conditions to an authorization of an access to the corresponding set-wise partition.

5 . The processor of claim 1 , wherein, for each set-wise partition of multiple set-wise partitions, the first one or more registers are to identify a respective plurality of addresses as corresponding to the set-wise partition.

6 . The processor of claim 1 , wherein the second one or more registers comprise a first register comprising multiple fields which correspond to different processor execution resources, respectively; and
wherein, for each of the multiple fields, the field is to provide a value indicating one or more types of ways as being available to be allocated to the corresponding processor execution resource.

7 . The processor of claim 6 , wherein the multiple fields comprise a first field which corresponds to one of a core, a thread, or a class of service.

8 . The processor of claim 1 , wherein the first circuitry to identify the cache line comprises the first circuitry to:
determine that the first address corresponds to a first set of a first set-wise partition; identify an offset between the first set and a first base of the first set-wise partition; detect an association of the memory access request with a second set-wise partition; and based on each of the association, the offset, and a second base of the second set-wise partition, identify a second set of the second set-wise partition.

9 . A system comprising:
a processor comprising:
a first one or more registers to provide first information which describes a set-wise partitioning of a cache;
a second one or more registers to provide second information which describes a way-wise partitioning of the cache; and
first circuitry coupled to the first one or more registers and the second one or more registers, the first circuitry to:
receive a memory access request comprising a first address; and
identify a cache line of the cache based on the first address, the set-wise

partitioning, and the way-wise partitioning;
wherein:
the first one or more registers comprise a first plurality of registers which correspond to different ones of multiple set-wise partitions, respectively;
the cache comprises multiple segments which each comprise a same total number of sets; and
for each of the first plurality of registers, the register is to provide a respective first set of bits which is to identify one or more of the multiple segments as belonging to the corresponding set-wise partition; and
a memory coupled to the processor, the memory to store a set of instructions which are to be executed with the processor.

10 . The system of claim 9 , wherein, for each of the first plurality of registers, the register is to further provide a respective second set of bits which is to indicate a base of the corresponding set-wise partition.

11 . The system of claim 9 , wherein, for each set-wise partition of multiple set-wise partitions, the first one or more registers are to identify a respective plurality of addresses as corresponding to the set-wise partition.

12 . The system of claim 9 , wherein the second one or more registers comprise a first register comprising multiple fields which correspond to different processor execution resources, respectively; and
wherein, for each of the multiple fields, the field is to provide a value indicating one or more types of ways as being available to be allocated to the corresponding processor execution resource.

13 . The system of claim 9 , wherein the first circuitry to identify the cache line comprises the first circuitry to:
determine that the first address corresponds to a first set of a first set-wise partition; identify an offset between the first set and a first base of the first set-wise partition; detect an association of the memory access request with a second set-wise partition; and based on each of the association, the offset, and a second base of the second set-wise partition, identify a second set of the second set-wise partition.

14 . A method at a processor, the method comprising:
accessing a first one or more registers to determine a set-wise partitioning of a cache; accessing a second one or more registers to determine a way-wise partitioning of the cache; receiving a memory access request comprising a first address; and identifying a cache line of the cache based on the first address, the set-wise partitioning, and the way-wise partitioning;
wherein:
the first one or more registers comprise a first plurality of registers which correspond to different ones of multiple set-wise partitions, respectively;
the cache comprises multiple segments which each comprise a same total number of sets; and
for each of the first plurality of registers, the register is to provide a respective first set of bits which is to identify one or more of the multiple segments as belonging to the corresponding set-wise partition.

15 . The method of claim 14 , wherein, for each set-wise partition of multiple set-wise partitions, the first one or more registers are to identify a respective plurality of addresses as corresponding to the set-wise partition.

16 . The method of claim 14 , wherein the second one or more registers comprise a first register comprising multiple fields which correspond to different processor execution resources, respectively; and
wherein, for each of the multiple fields, the field is to provide a value indicating one or more types of ways as being available to be allocated to the corresponding processor execution resource.

17 . The method of claim 14 , wherein identifying the cache line comprises:
determining that the first address corresponds to a first set of a first set-wise partition; identifying

Assignees

• Intel Corp

Inventors

• Abraham Philip
• Van Doren Stephen
• Gupta Ritu
• Herdrich Andrew

Classifications

• G06F12/0846

  Cache with multiple tag or data arrays being simultaneously accessible · CPC title

• G06F12/084

  with a shared cache · CPC title

• G06F12/0855

  Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence) · CPC title

• G06F12/0895

  of parts of caches, e.g. directory or tag array · CPC title

• G06F2212/1041

  Resource optimization · CPC title