Read and write address translation using reserved memory pages for multi-page translation units

Patent metadata

Field	Value
Publication number	US-12487916-B2
Application number	US-202318475966-A
Country	US
Kind code	B2
Filing date	Sep 27, 2023
Priority date	Nov 8, 2022
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

In some implementations, a memory device may receive a write command that includes data to be written to multiple memory pages of a translation unit (TU) of the memory device. The multiple memory pages of the TU may span multiple memory planes of the memory device. The memory device may identify the multiple memory pages of the TU, to which the data is to be written, based on one or more bad blocks of the memory device and a determination of whether one or more memory pages of the memory device are to be reserved. The memory device may write the data to the multiple memory pages of the TU.

First claim

What is claimed is:

1 . A memory device, comprising:
one or more components configured to:
identify a translation unit (TU) associated with a read command, wherein the TU includes multiple memory pages that span multiple memory planes of the memory device;
identify an initial memory page of the multiple memory pages of the TU based on a logical-to-physical mapping table, wherein the initial memory page is included in a first memory plane of the multiple memory planes;
identify one or more additional memory pages included in the multiple memory pages of the TU based on the initial memory page and based on an indication of one or more bad blocks of the memory device,
wherein the one or more additional memory pages are included in one or more additional memory planes of the multiple memory planes, and
wherein the one or more components, to identify the one or more additional memory pages of the TU, are configured to:
identify a first page index value that identifies the initial memory page;
determine, based on the indication of the one or more bad blocks of the memory device, a set of page index values that indicate a set of bad pages of the memory device;
identify a second page index value that is closest to the first page index value out of all page index values, included in the set of page index values, that are greater than the first page index value;
determine whether the second page index value is within an offset threshold of the first page index value; and
identify the one or more additional memory pages of the TU based on whether the second page index value is within the offset threshold of the first page index value; and

read data from the initial memory page and the one or more additional memory pages included in the TU.

2 . The memory device of claim 1 , wherein all memory pages included in the TU are included in a single multi-plane page stripe and a single multi-plane block stripe.

3 . The memory device of claim 1 , wherein at least one memory page of the TU is included in a first multi-plane page and at least one other memory page of the TU is included in a second multi-plane page.

4 . The memory device of claim 1 , wherein all memory pages included in the TU are unreserved memory pages, and
wherein a multi-plane page stripe, that includes the TU, includes one or more reserved memory pages to which user data is not to be written.

5 . The memory device of claim 4 , wherein the one or more reserved memory pages is a quantity of reserved memory pages, located at an end of the multi-plane page stripe, that is less than a quantity of memory pages included in the TU.

6 . The memory device of claim 5 , wherein the quantity of reserved memory pages located at the end of the multi-plane page stripe is based on a quantity of bits stored per memory cell included in the multi-plane page stripe.

7 . The memory device of claim 4 , wherein the one or more components are further configured to:
detect a new bad block of the memory device; and mark a memory page, of the one or more reserved memory pages, as an unreserved memory page based on detecting the new bad block,
wherein marking the memory page as an unreserved memory page enables the memory device to write user data to the memory page.

8 . The memory device of claim 1 , wherein the one or more components, to identify the one or more additional memory pages of the TU, are configured to:
identify the one or more additional memory pages of the TU as one or more sequential memory pages based on a determination that the second page index value is not within the offset threshold of the first page index value,
wherein the initial memory page and the one or more sequential memory pages have consecutive page index values.

9 . The memory device of claim 1 , wherein the one or more components, to identify the one or more additional memory pages of the TU, are configured to:
identify the one or more additional memory pages of the TU as one or more non-sequential memory pages based on a determination that the second page index value is within the offset threshold of the first page index value,
wherein the initial memory page and the one or more non-sequential memory pages have at least one non-consecutive page index value.

10 . The memory device of claim 1 , wherein the offset threshold is based on a quantity of memory pages included in the TU.

11 . The memory device of claim 1 , wherein the indication of the one or more bad blocks of the memory device includes a data structure that stores an indication of a set of page index values corresponding to a set of pages that are included in the one or more bad blocks.

12 . The memory device of claim 11 , wherein, for memory cells that store two or more bits per memory cell, the data structure stores an indication of only an initial page per plane for each plane that includes a bad block.

13 . A memory device, comprising:
one or more components configured to:
identify a translation unit (TU) associated with a read command, wherein the TU includes multiple memory pages that span multiple memory planes of the memory device;
identify an initial memory page of the multiple memory pages of the TU based on a logical-to-physical mapping table, wherein the initial memory page is included in a first memory plane of the multiple memory planes;
determine a plane index value of the first memory plane;
identify one or more additional memory pages included in the multiple memory pages of the TU based on the initial memory page and based on the plane index value,
wherein the one or more additional memory pages are included in one or more additional memory planes of the multiple memory planes, and
wherein the one or more components, to identify the one or more additional memory pages of the TU, are configured to:
determine that the plane index value satisfies a first condition; and
identify the one or more additional memory pages of the TU as one or more sequential memory pages based on determining that the plane index value satisfies the first condition, wherein the initial memory page and the one or more sequential memory pages are sequential; and

read data from the initial memory page and the one or more additional memory pages included in the TU.

14 . The memory device of claim 13 , wherein the one or more components are further configured to:
refrain from performing a bad block search when identifying the one or more additional memory pages of the TU based on determining that the plane index value satisfies the first condition.

15 . The memory device of claim 13 , wherein the first condition is that the plane index value is an even number.

16 . The memory device of claim 13 , wherein all memory pages included in the TU are included in a single multi-plane page stripe and a single multi-plane block stripe.

17 . The memory device of claim 13 , wherein all memory pages included in the TU are unreserved memory pages, and
wherein a multi-plane page stripe, that includes the TU, includes one or more reserved memory pages to which user data is not to be written.

18 . A memory device, comprising:
one or more components configured to:
identify a translation unit (TU) associated with a read command, wherein the TU includes multiple memory pages that span multiple memory planes of the memory device;
identify an initial memory page of the multiple memory pages of the TU based on a logical-to-physical mapping table, wherein the initial memory page is included in a first memory plane of the multiple memory pla

Assignees

• Micron Technology Inc

Inventors

• Wei Meng

Classifications

• G06F2212/7204

  Capacity control, e.g. partitioning, end-of-life degradation · CPC title

• G06F2212/7203

  Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title