Bonding multiple peripheral ports to a single virtual machine

Patent metadata

Field	Value
Publication number	US-12487846-B1
Application number	US-202218067444-A
Country	US
Kind code	B1
Filing date	Dec 16, 2022
Priority date	Dec 16, 2022
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

An input/output (I/O) device is coupled to a processor via a first peripheral bus and a second peripheral bus. The I/O device is configured to expose a first physical function (PF) and a second PF to a virtual machine (VM) executing on the processor. A first virtual function (VF) associated with the first PF is assigned to the first peripheral bus, and a second VF associated with the second PF is assigned to the second peripheral bus. The first VF and the second VF are exposed as a single VF to the VM. The VM can perform transactions with the I/O device via the single VF using the first peripheral bus and the second peripheral bus.

First claim

What is claimed is:

1 . A method executed by a processor comprising:
configuring an input/output (I/O) device to expose a first physical function (PF) and a second PF to a virtual machine (VM) executing on the processor, the I/O device coupled to the processor via a first peripheral bus and a second peripheral bus; assigning a first virtual function (VF) associated with the first PF to the first peripheral bus; assigning a second VF associated with the second PF to the second peripheral bus; configuring the first VF and the second VF to be exposed as a single VF to the VM; and performing transactions by the VM with the I/O device via the single VF using the first peripheral bus and the second peripheral bus.

2 . The method of claim 1 , wherein a first I/O memory space allocated to the first VF in the I/O device, and a second I/O memory space allocated to the second VF in the I/O device are mapped to an address space allocated to the VM.

3 . The method of claim 2 , wherein the first I/O memory space allocated to the first VF includes a first set of queues that are associated with the first peripheral bus, and the second I/O memory space allocated to the second VF includes a second set of queues that are associated with the second peripheral bus.

4 . The method of claim 3 , wherein performing the transactions by the VM includes:
configuring ingress queues in the first set of queues to send, via the first peripheral bus, first payload data for a first set of packets received by the I/O device for ingress traffic; and configuring ingress queues in the second set of queues to send, via the second peripheral bus, second payload data for a second set of packets received by the I/O device for the ingress traffic.

5 . The method of claim 4 , wherein the first payload data and the second payload data are written in a memory space allocated to the VM in a system memory at physical addresses associated with the memory space allocated to the VM, wherein the physical addresses are translated from virtual addresses associated with the first VF and the second VF by a first I/O memory management unit (IOMMU) coupled to the first peripheral bus and a second IOMMU coupled to the second peripheral bus, respectively.

6 . The method of claim 4 , wherein the ingress traffic is split on the first peripheral bus and the second peripheral bus based on a split scheme that includes applying a hash function to header fields of each packet in the first set of packets and the second set of packets.

7 . The method of claim 4 , wherein the I/O device is a network device, and wherein the first set of packets sent via the first peripheral bus is received via a network on a first Ethernet port of the I/O device, and the second set of packets sent via the second peripheral bus is received via the network on a second Ethernet port of the I/O device.

8 . The method of claim 4 , wherein performing the transactions by the VM further includes:
configuring sub-completion queues in the first set of queues to send completion messages on the first peripheral bus corresponding to the first set of packets sent via the ingress queues in the first set of queues; and configuring sub-completion queues in the second set of queues to send completion messages on the second peripheral bus corresponding to the second set of packets sent via the ingress queues in the second set of queues.

9 . The method of claim 3 , wherein performing the transactions by the VM includes:
configuring egress queues in the first set of queues to receive a portion of payload data associated with a read transaction via the first peripheral bus; and configuring egress queues in the second set of queues to receive a remaining portion of the payload data associated with the read transaction via the second peripheral bus, wherein the read transaction is performed to read the payload data from a memory space allocated to the VM in a system memory to transmit one or more packets by the I/O device for egress traffic.

10 . The method of claim 1 , wherein virtual addresses and interrupts associated with the first VF and the second VF are mapped to the VM by a first IOMMU coupled to the first peripheral bus and a second IOMMU coupled to the second peripheral bus, respectively.

11 . The method of claim 1 , wherein configuring the first VF and the second VF to be exposed as the single VF to the VM includes mirroring configurations between a first set of configuration registers assigned to the first VF in an address space allocated to the VM, and a second set of configuration registers assigned to the second VF in the address space allocated to the VM.

12 . The method of claim 11 , wherein the first set of configuration registers includes a first set of registers assigned to message-signaled interrupts associated with the first VF, and the second set of configuration registers includes a second set of registers assigned to message-signaled interrupts associated with the second VF, and wherein the first set of registers and the second set of registers are configured to generate same message signaled interrupts to the VM.

13 . A computing system, comprising:
a host processor configured to execute a virtual machine (VM) and allocate an address space to the VM; a network device coupled to the host processor via a first peripheral component interconnect express (PCIe) bus and a second PCIe bus, the network device having a single-root input/output virtualization (SR-IOV) capability to expose multiple functions comprising physical functions (PFs), and one or more virtual functions (VFs) associated with each PF; a first input/output memory management unit (IOMMU) coupled to the network device via the first PCIe bus; and a second IOMMU coupled to the network device via the second PCIe bus, wherein the host processor is operable to:
configure the network device to expose a first physical function (PF) and a second PF to the VM;
assign a first VF associated with the first PF to the first PCIe bus;
assign a second VF associated with the second PF to the second PCIe bus; and
configure the first VF and the second VF to be exposed as a single VF to the VM, and
wherein the VM is operable to:
perform transactions with the network device via the single VF using the first PCIe bus and the second PCIe bus.

14 . The computing system of claim 13 , wherein the network device comprises:
a first set of queues associated with the first VF that are mapped to the address space allocated to the VM, wherein the first IOMMU is configured to translate virtual addresses of transactions processed by the first set of queues to physical addresses corresponding to a memory space allocated to the VM in a system memory; and a second set of queues associated with the second VF that are mapped to the address space allocated to the VM, wherein the second IOMMU is configured to translate virtual addresses of transactions processed by the second set of queues to physical addresses corresponding to the memory space allocated to the VM in the system memory.

15 . The computing system of claim 14 , wherein the first set of queues are configured to send payload data, completion messages, and message-signaled interrupts associated with the first VF on the first PCIe bus, and the second set of queues are configured to send payload data, completion messages, and message-signaled interrupts associated with the second VF on the second PCIe bus.

16 . The computing system of claim 13 , wherein configuring the first VF and the second VF to be exposed as the single VF to the VM includes

Assignees

• Amazon Tech Inc

Inventors

• Bshara Said
• Schmeilin Evgeny
• Sironi Filippo
• Serebrin Benjamin

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F2009/45583

  Memory management, e.g. access or allocation · CPC title

• G06F2009/45579

  I/O management, e.g. providing access to device drivers or storage · CPC title

• G06F2213/0026

  PCI express · CPC title

• G06F9/45558 Primary

  Hypervisor-specific management and integration aspects · CPC title