Equipment design and testing using in-situ on-die time-domain reflectometry

Patent metadata

Field	Value
Publication number	US-12487268-B2
Application number	US-202318128942-A
Country	US
Kind code	B2
Filing date	Mar 30, 2023
Priority date	Mar 30, 2023
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

Using “in-situ on-die time-domain reflectometry (TDR)” with data signal paths of integrated circuits, printed circuit boards, and data processing equipment and systems allows testing, verification and troubleshooting of data channel signal path impedance variations including the package, escape routing, socket, board, and cable/connectors provides fast characterization thereof. Operation of “in-situ on-die TDR” uses existing analog-to-digital converter (ADC) and data transmitter (TX) drivers of an integrated circuit to act as a TDR sampling head by performing a user interface-based TDR sampling with a step-waveform generated by an integrated circuit TX driver. Then sampling the step-waveform with the ADC of the integrated circuit using spline interpolation to obtain the over-sampled waveform. Once the sampled step-waveform is obtained, the TDR profile of the sampled data channels may be calculated. Large amounts of impedance variation data may thus be collected during either integrated circuit manufacturer or customer-built data communications channel testing.

First claim

What is claimed is:

1 . A method of using in-situ on-die time-domain reflectometry (TDR) for testing an integrated circuit equipment communications channel, comprising:
sending a data pattern to a driver of a transmitter to generate a step waveform at a transmit node; coupling an analog-to-digital converter (ADC) of a receiver to a circuit node of a data circuit under test; opening a connection to the data circuit to obtain an open circuit step voltage when applying the step waveform to the transmit node; determining an output resistance of the transmit node with a measurement sample rate of less than two (2) gigahertz; terminating an output of the data circuit under test; applying the step waveform to the data circuit under test to measure a time varying detected voltage with the ADC of the receiver; and calculating a time varying load impedance from the time varying detected voltage, the open circuit step voltage and the output resistance of the transmit node.

2 . The method according to claim 1 , further comprising doing a loop back test of the transmit node with the ADC of the receiver using the step waveform.

3 . The method according to claim 1 , further comprising normalizing the time varying detected voltage with the time varying detected voltage measured at time zero (0).

4 . The method according to claim 1 , wherein the time varying load impedance is determined using equation:

Z
L

(
t
)

=

V
detected

(
t
)

V
step

-

V
detected

(
t
)

*

R
src

where Z L (t) represents the time varying load impedance, V detected (t) represents the time varying detected voltage, V step represents the open circuit step voltage at the transmit node, and R src represents a real part of an output impedance of the transmit node.

5 . The method according to claim 1 , wherein resolution of the ADC is 6-bit.

6 . The method according to claim 1 , wherein resolution of the ADC is 7-bit.

7 . The method according to claim 1 , wherein the ADC is oversampled.

8 . The method according to claim 1 , further comprising determining a location of the time varying load impedance based upon a measured time.

9 . The method according to claim 1 , further comprising determining a plurality of locations of time varying load impedances based upon a plurality of respective measured times.

10 . The method according to claim 1 , further comprising determining a location of an open circuit fault on a data transmission circuit coupled to the transmit node by measuring a time when the time varying load impedance increases.

11 . The method according to claim 1 , further comprising determining a location of a short circuit fault on a data transmission circuit coupled to the transmit node by measuring a time when the time varying load impedance decreases.

12 . An integrated circuit data transceiver (transmitter/receiver) having in-situ on-die time-domain reflectometry (TDR) circuits for testing a data communications channel while coupled to the data communications channel, comprising:
a data driver coupled to a transmit node; a near-end ADC (analog-to-digital converter) adapted for coupling to the transmit node; a far-end ADC adapted for coupling to a receive node; and data signal connections adapted for coupling the transmit and receive nodes to the data communications channel; wherein
when in a TDR test mode, the data driver provides a step waveform to the transmit node and the near-end ADC for monitoring a time varying voltage at the transmit node, and
when in an operational mode, the data driver transmits data to the transmit node and the far-end ADC, at the receive node, receives the data.

13 . The integrated circuit data transceiver according to claim 12 , wherein the integrated circuit data transceiver further comprises a data serializer/deserializer (serdes).

14 . The integrated circuit data transceiver according to claim 12 , wherein the integrated circuit data transceiver further comprises a data multiplexer for switching the near-end ADC between the receive node and the transmit node during a loop back test.

15 . A data communications system, comprising:
an integrated circuit data transceiver (transmitter/receiver) having in-situ on-die time-domain reflectometry (TDR) circuits, wherein the integrated circuit data transceiver comprises
a data driver coupled to a transmit node,
a near-end analog-to-digital converter (ADC) adapted for coupling to either the transmit node,
a far-end ADC adapted for coupling to a receive node,
data signal connections adapted for coupling the transmit and receive nodes to a data communications channel,
the data communications channel comprises at least one data communications cable coupled to the data signal connections, and
at least one network adapter coupled to the at least one data communications cable and having receive and transmit capabilities, wherein
when in a TDR test mode, the data driver provides a step waveform to the transmit node and the near-end ADC for monitoring a time varying voltage at the transmit node, and
when in an operational mode, the data driver transmits data to the transmit node and the far-end ADC, at the receive node, receives the data.

16 . The data communications system according to claim 15 , further comprising a second network adapter coupled between the data signal connections and one of the at least one data communications cable.

17 . The data communications system according to claim 15 , wherein the at least one data communications cable is at least one coaxial cable.

18 . The data communications system according to claim 15 , wherein the at least one data communications cable is at least one twisted-pair cable.

19 . The data communications system according to claim 15 , wherein the at least one twisted-pair cable is at least one Ethernet cable.

20 . The data communications system according to claim 15 , further comprising a plurality of network adapters coupled between the data signal connections and a plurality of data communications cable.

Assignees

• Xilinx Inc

Inventors

• Wu Zhaoyin Daniel
• Fang Tianyu
• Chou Chuen-Huei
• Borrelli Christopher J
• Zhang Geoffrey

Classifications

• G01R31/52 Primary

  Testing for short-circuits, leakage current or ground faults · CPC title

• G01R31/11 Primary

  using pulse reflection methods · CPC title