Array substrate, display panel and display device

Patent metadata

Field	Value
Publication number	US-12484408-B2
Application number	US-202318341064-A
Country	US
Kind code	B2
Filing date	Jun 26, 2023
Priority date	Feb 24, 2021
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

An array substrate including: pixel circuits; first signal lines including first-type signal lines and second-type signal lines, each second-type signal line includes a first segment and a second segment separated by a hole area; first connection signal lines, at least a number of the plurality of first connection signal lines is located in a display area, each first connection signal line includes a first connection segment, a second connection segment and a third connection segment connected to each other; first compensation signal lines; an orthographic projection of the first connection signal lines on a plane where the array substrate is located does not overlap with an orthographic projection of the pixel circuits on the plane, and an orthographic projection of the first compensation signal lines on the plane does not overlap with the orthographic projection of the pixel circuits on the plane.

First claim

What is claimed is:

1 . An array substrate comprising a hole area and a display area surrounding the hole area, wherein the array substrate comprises:
a plurality of pixel circuits distributed in an array in the display area; a plurality of first signal lines electrically connected to the pixel circuits and extending along a first direction, wherein the plurality of first signal lines comprise a plurality of first-type signal lines and a plurality of second-type signal lines, and each of the second-type signal lines comprises a first segment and a second segment separated by the hole area; a plurality of first connection signal lines, wherein at least a number of the plurality of first connection signal lines is located in the display area, each of the first connection signal lines comprises a first connection segment, a second connection segment and a third connection segment connected to each other, the first connection segment is electrically connected to the first segment, the third connection segment is electrically connected to the second segment, the second connection segment is connected between the first connection segment and the third connection segment, both the first connection segment and the third connection segment extend along a second direction, and the second connection segment extends along the first direction; a plurality of first compensation signal lines, wherein the plurality of first compensation signal lines are located in the display area, the plurality of first compensation signal lines comprise a plurality of first-type compensation signal lines and a plurality of second-type compensation signal lines, the first-type compensation signal lines extend along the first direction, and the second-type compensation signal lines extend along the second direction; wherein an orthographic projection of the first connection signal lines on a plane where the array substrate is located does not overlap with an orthographic projection of the pixel circuits on the plane, an orthographic projection of the first compensation signal lines on the plane does not overlap with the orthographic projection of the pixel circuits on the plane, the first-type compensation signal lines are configured to compensate an uneven density of the first connection signal lines in the display area in the first direction, and the second-type compensation signal lines are configured to compensate an uneven density of the first connection signal lines in the display area in the second direction.

2 . The array substrate according to claim 1 , wherein in the second direction, a line spacing between adjacent first-type compensation signal lines is equal to a line spacing between adjacent second connection segments, and a line width of each of the first-type compensation signal lines is equal to a line width of the second connection segment.

3 . The array substrate according to claim 1 , wherein, in the first direction, a line spacing between adjacent second-type compensation signal lines, a line spacing between adjacent first connection segments and a line spacing between adjacent third connection segments are equal, and a line width of each of the second-type compensation signal lines, a line width of the first connection segment and a line width of the third connection segment are equal.

4 . The array substrate according to claim 1 , wherein the array substrate further comprises:
a plurality of first fixed voltage signal lines electrically connected to the pixel circuits and extending along the first direction; a plurality of second fixed voltage signal lines electrically connected to the pixel circuits and extending along the second direction; wherein the first-type compensation signal lines are electrically connected to the second fixed voltage signal lines, and the second-type compensation signal lines are electrically connected to the first fixed voltage signal lines.

5 . The array substrate according to claim 4 , wherein the first fixed voltage signal lines and the second fixed voltage signal lines are located in different film layers, the second connection segment, the first-type compensation signal lines and the first signal lines are arranged to be in a same layer and have a same material, and the first connection segment, the third connection segment, and the second-type compensation signal lines are arranged to be in a same layer and have a same material.

6 . The array substrate according to claim 1 , wherein the hole area has a centerline in the second direction, the smaller a vertical distance in the second direction between each of the second-type signal lines and the centerline, the smaller a vertical distance in the second direction between the centerline and the second connection segment electrically connected to the second-type signal line, and the smaller a vertical distance in the second direction between each of the second-type signal lines and the centerline, the smaller a vertical distance in the second direction between the centerline and the first connection segment electrically connected to the second-type signal line and a vertical distance in the second direction between the centerline and the third connection segment electrically connected to the second-type signal line.

7 . The array substrate according to claim 6 , wherein a number of pixel circuits arranged along the second direction in an interval between every two adjacent second connection segments on a same side of the hole area is equal, and a number of pixel circuits arranged along the first direction in an interval between adjacent first connection segments is equal to a number of pixel circuits arranged along the first direction in an interval between adjacent third connection segments;
on a same side of the hole area, a number of pixel circuits arranged along the second direction in an interval between adjacent second connection segments is twice a number of pixel circuits arranged along the first direction in an interval between adjacent first connection segments.

8 . The array substrate according to claim 7 , wherein pixel circuits arranged along the second direction in an interval between adjacent second connection segments are arranged to be immediately adjacent to each other, and pixel circuits arranged along the second direction in an interval between adjacent first-type compensation signal lines are arranged to be immediately adjacent to each other.

9 . The array substrate according to claim 1 , wherein the first direction is a column direction, the second direction is a row direction, and the first signal lines are data signal lines; or the first direction is a row direction, the second direction is a column direction, and the first signal lines are scanning signal lines or light-emitting control signal lines or reference voltage signal lines.

10 . The array substrate according to claim 1 , wherein the first direction is a column direction, the second direction is a row direction, the first signal lines are data signal lines, and the array substrate further comprises:
a plurality of second signal lines, wherein the second signal lines are scanning signal lines or light-emitting control signal lines or reference voltage signal lines, the second signal lines are electrically connected to the pixel circuits and extend along the second direction, the plurality of second signal lines comprise a plurality of third-type signal lines and a plurality of fourth-type signal lines, each of the fourth-type signal lines comprises a third segment and a fourth segment separated by the hole area; a plurality of second connection signal lines, wherein at least a number of the plurality of second connection signal lines is located in the di

Assignees

• Hefei Visionox Tech Co Ltd

Inventors

• Feng Hongqing
• Li Hongrui
• Zeng Xiangtao
• Qin Shaoyang
• Zhao Chengyu
• Wang Shoukun

Classifications

• H10K59/65

  OLEDs integrated with inorganic image sensors · CPC title

• H10K59/60

  OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G3/3275

  Details of drivers for data electrodes · CPC title

• H10K59/121

  characterised by the geometry or disposition of pixel elements · CPC title