Display panel and display device

Patent metadata

Field	Value
Publication number	US-12484407-B2
Application number	US-202318333280-A
Country	US
Kind code	B2
Filing date	Jun 12, 2023
Priority date	Oct 16, 2020
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

The present disclosure provides a display panel and a display device. The display panel includes: a base substrate, on which a first metal layer and a second metal layer are stacked; and organic light emitting diode devices on a side, away from the base substrate, of the first metal layer. The first metal layer includes a power signal line. The power signal line is electrically connected with the second electrode layer in a peripheral area. Each organic light-emitting diode device includes a first electrode layer, a light emitting layer and a second electrode layer which are sequentially arranged on the base substrate. The second power signal line includes traces in a first direction and traces in a second direction, and orthographic projections of the traces in the first direction on the base substrate are intersected with orthographic projections of the traces in the second direction on the base substrate.

First claim

What is claimed is:

1 . A display panel, comprising:
a base substrate, on which an active layer, a first insulating layer, a first gate layer, a second gate layer, and a first metal layer are stacked; and an organic light emitting diode device arranged on a side, away from the base substrate, of the first metal layer, the organic light emitting diode device comprising a first electrode layer, a light emitting layer and a second electrode layer which are sequentially arranged on the base substrate, wherein the first gate layer comprises a plurality of first energy storage capacitor plates, the second gate layer comprises a plurality of second energy storage capacitor plates, the first energy storage capacitor plates are in one-to-one correspondence with the second energy storage capacitor plates, each first energy storage capacitor plate and the second energy storage capacitor plate corresponding to said each first energy storage capacitor plate form an energy storage capacitor, an orthographic projection of each first energy storage capacitor plate on the base substrate is within an outline of an orthographic projection of the second energy storage capacitor plate, corresponding to said each first energy storage capacitor plate, on the base substrate, the second energy storage capacitor plates are independent from each other, and adjacent ones of the second energy storage capacitor plates are spaced apart from each other, the first metal layer comprises a second power signal line, and the second power signal line comprises at least one trace extending in a second direction, the organic light emitting diode device belongs to one sub-pixel unit, the sub-pixel unit corresponds to the at least one trace extending in the second direction, the at least one trace extending in the second direction corresponding to the sub-pixel unit is arranged uniformly along a first direction, orthographic projections of the first direction and the second direction on the base substrate are intersected with each other, each of the first electrode layer, the light emitting layer and the second electrode layer of the organic light emitting diode device is symmetrical with respect to a symmetry axis of the at least one trace extending in the second direction corresponding to the sub-pixel unit which the organic light emitting diode device belongs to, the symmetry axis extends in the second direction.

2 . The display panel of claim 1 , further comprising:
a data signal line, wherein an orthographic projection of the data signal line on the base substrate is not overlapped with orthographic projections of the second energy storage capacitor plates on the base substrate.

3 . The display panel of claim 2 , further comprising:
a first power signal line and a second power signal line, wherein the first power signal line and the second power signal line are arranged in different layers.

4 . The display panel of claim 3 , wherein the second power signal line comprises a plurality of traces in a first direction and a plurality of traces in a second direction, orthographic projections of the traces in the first direction on the base substrate are intersected with orthographic projections of the traces in the second direction on the base substrate.

5 . The display panel of claim 4 , wherein the traces in the first direction and the traces in the second direction are disposed in a same layer.

6 . The display panel of claim 5 , wherein, in a display area, the orthographic projections of the traces in the second direction on the base substrate are overlapped with an orthographic projection of the second gate layer on the base substrate.

7 . The display panel of claim 5 , wherein M sub-pixel units are provided between every two adjacent traces in the first direction;
N sub-pixel units are provided between every two adjacent traces in the second direction; and M and N are positive integers.

8 . The display panel of claim 4 , further comprising:
an initialization voltage signal line, wherein, in a display area, the orthographic projections of the traces in the first direction on the base substrate are overlapped with an orthographic projection of the initialization voltage signal line on the base substrate.

9 . The display panel of claim 8 , wherein, in the display area, the orthographic projections of the traces in the second direction on the base substrate are overlapped with an orthographic projection of the second gate layer on the base substrate.

10 . The display panel of claim 8 , wherein M sub-pixel units are provided between every two adjacent traces in the first direction;
N sub-pixel units are provided between every two adjacent traces in the second direction; and M and N are positive integers.

11 . The display panel of claim 4 , wherein, in a display area, the orthographic projections of the traces in the first direction on the base substrate are overlapped with an orthographic projection of the first power signal line on the base substrate.

12 . The display panel of claim 11 , wherein, in the display area, the orthographic projections of the traces in the second direction on the base substrate are overlapped with an orthographic projection of the second gate layer on the base substrate.

13 . The display panel of claim 11 , wherein M sub-pixel units are provided between every two adjacent traces in the first direction;
N sub-pixel units are provided between every two adjacent traces in the second direction; and M and N are positive integers.

14 . The display panel of claim 4 , wherein, in a display area, the orthographic projections of the traces in the first direction on the base substrate are overlapped with an orthographic projection of the data signal line on the base substrate.

15 . The display panel of claim 14 , wherein, in the display area, the orthographic projections of the traces in the second direction on the base substrate are overlapped with an orthographic projection of the second gate layer on the base substrate.

16 . The display panel of claim 14 , wherein M sub-pixel units are provided between every two adjacent traces in the first direction;
N sub-pixel units are provided between every two adjacent traces in the second direction; and M and N are positive integers.

17 . The display panel of claim 4 , wherein, in a display area, the orthographic projections of the traces in the second direction on the base substrate are overlapped with an orthographic projection of the second gate layer on the base substrate.

18 . The display panel of claim 4 , wherein M sub-pixel units are provided between every two adjacent traces in the first direction;
N sub-pixel units are provided between every two adjacent traces in the second direction; and M and N are positive integers.

19 . The display panel of claim 1 , further comprising:
a plurality of organic light emitting diode devices, wherein each of the organic light emitting diode devices comprises a first electrode layer, a light emitting layer and a second electrode layer which are sequentially arranged on the base substrate.

20 . A display device, comprising the display panel of claim 1 .

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zhu Jianchao

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• H10K59/1201

  Manufacture or treatment · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title