Display panel and method for fabricating same

Patent metadata

Field	Value
Publication number	US-12484243-B2
Application number	US-202217994031-A
Country	US
Kind code	B2
Filing date	Nov 25, 2022
Priority date	Sep 29, 2022
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

A method for fabricating a display panel includes: forming a plurality of N-type doped amorphous silicon structures on a substrate; forming an amorphous silicon layer covering the N-type doped amorphous silicon structures and the substrate; blue laser annealing the amorphous silicon layer and the N-type doped amorphous silicon structures, so that the N-type doped amorphous silicon structures are converted into N-type heavily doped polysilicon structures, a part of the amorphous silicon layer in contact with one of the N-type doped amorphous silicon structures and located between two adjacent N-type doped amorphous silicon structures is converted into an N-type lightly doped polysilicon structure, and other parts of the amorphous silicon layer are converted into a polysilicon layer; and patterning the polysilicon layer to form a semiconductor layer.

First claim

What is claimed is:

1 . A method for fabricating a display panel, comprising:
forming a plurality of N-type doped amorphous silicon structures on a substrate; forming an amorphous silicon layer covering the N-type doped amorphous silicon structures and the substrate; blue laser annealing the amorphous silicon layer and the N-type doped amorphous silicon structures, so that the N-type doped amorphous silicon structures are converted into N-type heavily doped polysilicon structures, a part of the amorphous silicon layer in contact with one of the N-type doped amorphous silicon structures and located between two adjacent N-type doped amorphous silicon structures is converted into an N-type lightly doped polysilicon structure, and other parts of the amorphous silicon layer are converted into a polysilicon layer; and patterning the polysilicon layer to form a semiconductor layer.

2 . The method for fabricating the display panel according to claim 1 , wherein the N-type doped amorphous silicon structures comprise a first N-type doped amorphous silicon structure and a second N-type doped amorphous silicon structure, and in the blue laser annealing the amorphous silicon layer and the N-type doped amorphous silicon structures, a laser scanning direction is a direction from the first N-type doped amorphous silicon structure to the second N-type doped amorphous silicon structure.

3 . The method for fabricating the display panel according to claim 2 , wherein a part of the amorphous silicon layer located on a side of the first N-type doped amorphous silicon structure close to the second N-type doped amorphous silicon structure and in contact with the first N-type doped amorphous silicon structure is converted into the N-type lightly doped polysilicon structure.

4 . The method for fabricating the display panel according to claim 3 , wherein the first N-doped amorphous silicon structure is converted into a first N-type heavily doped polysilicon structure, the second N-type doped amorphous silicon structure is converted into a second N-type doped polysilicon structure, the semiconductor layer comprises a channel portion located between the N-type lightly doped polysilicon structure and the second N-type heavily doped polysilicon structure, and the channel portion is in contact with the N-type lightly doped polysilicon structure and the second N-type heavily doped polysilicon structure.

5 . The method for fabricating the display panel according to claim 3 , further comprising:
forming a gate insulating layer on the semiconductor layer; forming a gate metal layer on the gate insulating layer, and patterning the gate metal layer to form a gate electrode; forming an interlayer dielectric layer on the gate electrode; forming a plurality of via holes penetrating through the interlayer dielectric layer, the gate insulating layer, and the semiconductor layer, and exposing the first N-type heavily doped polysilicon structure and the second N-type heavily doped polysilicon structure; and forming a source-drain electrode layer on the interlayer dielectric layer, and patterning the source-drain electrode layer to form a source electrode and a drain electrode, wherein the drain electrode is in contact with the first N-type heavily doped polysilicon structure through one of the via holes, and the source electrode is in contact with the second N-type heavily doped polysilicon structure through another via hole.

6 . The method for fabricating the display panel according to claim 5 , wherein an orthographic projection of the first N-type heavily doped polysilicon structure on the substrate does not overlap with an orthographic projection of the gate electrode on the substrate, and an orthographic projection of the N-type lightly doped polysilicon structure on the substrate partially overlaps the orthographic projection of the gate electrode on the substrate.

7 . The method for fabricating the display panel according to claim 6 , wherein a distance between the orthographic projection of the first N-type heavily doped polysilicon structure on the substrate and the orthographic projection of the gate electrode on the substrate is 1 μm to 3 μm, a length of the N-type lightly doped polysilicon structure is 1 μm to 4 μm, and a length of an overlapping portion of the orthographic projection of the N-type lightly doped polysilicon structure on the substrate and the orthographic projection of the gate electrode on the substrate is greater than 0 μm and less than or equal to 1 μm.

8 . The method for fabricating the display panel according to claim 1 , wherein each of the N-type doped amorphous silicon structures has an inclined sidewall and a bottom surface connected to the inclined sidewall and lying flat on the substrate, and an angle between the inclined sidewall and the bottom surface is less than 45°.

9 . The method for fabricating the display panel according to claim 8 , wherein a length of an orthographic projection of the inclined sidewall on the bottom surface is greater than or equal to 0.5 μm and less than or equal to 2 μm.

10 . The method for fabricating the display panel according to claim 1 , wherein in the blue laser annealing the amorphous silicon layer and the N-type doped amorphous silicon structures, crystallization energy is greater than or equal to 700 mA and less than or equal to 1200 mA.

Assignees

• Shenzhen China Star Optoelectronics Semiconductor Display Tech Co Ltd

Inventors

• Li Jinming

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6743

  Silicon · CPC title

• H10D30/6729

  characterised by the electrodes · CPC title

• H10D30/6706

  for preventing leakage current  (TFTs characterised by the properties of the source or drain H10D30/6713) · CPC title

• H10D30/6745

  Polycrystalline or microcrystalline silicon · CPC title