Self-calibrating buffered-voltage DAC

Patent metadata

Field	Value
Publication number	US-12483255-B2
Application number	US-202318479131-A
Country	US
Kind code	B2
Filing date	Oct 2, 2023
Priority date	Dec 12, 2022
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

A self-calibrated buffered-voltage DAC includes a DAC configured to receive an input digital signal and output a first analog voltage signal, a buffer amplifier configured to receive the first voltage signal from the DAC and provide a buffered second analog voltage signal, a voltage to frequency converter configured to selectively receive the first and second voltage signals and provide first and second output signals at respective first and second frequencies, a counter configured to receive the output signals from the voltage to frequency converter and provide respective first and second digital output signals corresponding to the respective first and second frequencies, a comparator configured to receive the first and second digital output signals and provide a digital calibration offset, and a DAC error code module configured to receive a digital input code and the digital calibration offset and to provide an offset corrected input digital signal to the DAC.

First claim

The invention claimed is:

1 . A self-calibrating buffered-voltage DAC circuit comprising:
a DAC configured to receive an input digital signal and output a first analog voltage signal; a buffer amplifier configured to receive the first analog voltage signal from the DAC and provide a buffered second analog voltage signal; a voltage to frequency converter configured to selectively receive the first analog voltage signal and the second analog voltage signal and provide first and second output signals at respective first and second frequencies; a counter configured to receive the first and second output signals from the voltage to frequency converter and provide respective first and second digital output signals corresponding to the respective first and second frequencies; a comparator configured to receive the first and second digital output signals and provide a digital calibration offset; and a DAC error code module configured to receive a digital input code and the digital calibration offset and to provide an offset corrected input digital signal to the DAC.

2 . The self-calibrating buffered-voltage DAC circuit of claim 1 , further comprising:
a first switch switchably connecting an output of the DAC to an input of the voltage to frequency converter; and a second switch switchably connecting an output of the buffer amplifier to the input of the voltage to frequency converter.

3 . The self-calibrating buffered-voltage DAC circuit of claim 2 , further comprising a controller configured to provide first and second switching signals to control operation of the respective first and second switches.

4 . The self-calibrating buffered-voltage DAC circuit of claim 3 , wherein the controller is configured to:
provide the first and second switching signals to open the first switch and close the second switch in a normal operation mode; and provide the first and second switching signals to sequentially open and close the first and second switches to sequentially provide the first and second voltage signals to the voltage to frequency converter in a calibration mode.

5 . The self-calibrating buffered-voltage DAC circuit of claim 1 , further comprising a clock signal generator configured to provide a clock signal at a clock signal frequency to the counter, the counter configured to provide the first and second digital output signals by dividing the clock signal frequency by the respective first and second frequencies.

6 . The self-calibrating buffered-voltage DAC circuit of claim 5 , further comprising a first frequency divider configured to divide the frequency of the clock signal to provide a divided clock signal to the counter.

7 . The self-calibrating buffered-voltage DAC circuit of claim 5 , further comprising a second frequency divider configured to divide the frequency of the first and second analog voltage signals and provide divided first and second output signals to the counter.

8 . The self-calibrating buffered-voltage DAC circuit of claim 1 , further comprising a memory module comprising first and second memory slots, the memory module configured to receive the first and second digital output signals and store the first and second digital output signals in the respective first and second memory slots.

9 . The self-calibrating buffered-voltage DAC circuit of claim 8 , wherein the comparator is configured to receive the first and second digital output signals from the respective first and second memory slots.

10 . The self-calibrating buffered-voltage DAC circuit of claim 8 , wherein the memory module comprises third and fourth switches configured to switchably connect the first and second digital output signals to the respective first and second memory slots.

11 . The self-calibrating buffered-voltage DAC circuit of claim 1 , wherein the comparator module is configured to calculate the digital calibration offset as a difference between the first and second digital output signals.

12 . The self-calibrating buffered-voltage DAC circuit of claim 1 , wherein the DAC error code module comprises a DAC error code logic module configured to:
compare the digital calibration offset to a predetermined minimum offset; output the digital calibration offset to the DAC input summing module if the digital calibration offset is not less than the predetermined minimum offset; and output a zero value to DAC input summing module if the digital calibration offset is less than the predetermined minimum offset.

13 . A method of calibrating a buffered-voltage DAC, the buffered-voltage DAC comprising a DAC configured to receive an input digital signal and provide a first analog voltage signal, and a buffer amplifier configured to receive the first analog voltage signal from the DAC and provide a buffered second analog voltage signal, the method comprising:
providing the first analog voltage signal to a voltage to frequency converter; measuring a first frequency from a first output of the voltage to frequency converter; providing the buffered second analog voltage signal to the voltage to frequency converter; measuring a second frequency from a second output of the voltage to frequency converter; calculating a difference between the first and second frequencies; determining a digital calibration offset from the difference; combining the digital calibration offset with an input digital signal to provide an offset corrected input digital signal; and providing the offset corrected input digital signal to the DAC.

14 . The method of claim 13 , further comprising:
connecting an output of the DAC to an input of the voltage to frequency converter with a first switch; and connecting an output of the buffer amplifier to the input of the voltage to frequency converter with a second switch.

15 . The method of claim 14 , further comprising:
providing, by a controller, first and second switching signals to control operation of the respective first and second switches.

16 . The method of claim 15 , wherein the controller:
provides the first and second switching signals to open the first switch and close the second switch in a normal operation mode; and provides the first and second switching signals to sequentially open and close the first and second switches to sequentially provide the first and second voltage signals to the voltage to frequency converter in a calibration mode.

17 . The method of claim 13 , further comprising:
receiving, by a counter, the first and second output signals from the voltage to frequency converter; providing, by the counter, respective first and second digital output signals corresponding to the respective first and second frequencies; receiving, by a memory module comprising first and second memory slots, the first and second digital output signals and storing the first and second digital output signals in the respective first and second memory slots; and receiving, by a comparator, the first and second digital output signals and providing the digital calibration offset.

18 . The method of claim 17 , wherein the comparator receives the first and second digital output signals from the respective first and second memory slots.

19 . The method of claim 17 , wherein the memory module connects the first and second digital output signals to the respective first and second memory slots via respective third and fourth switches.

20 . The method of claim 13 , further comprising:
comparing, by a logic module, the digital calibration offset to a predetermined

Assignees

• Nxp Bv

Inventors

• Zhang Yizhong
• Jin Jie
• Mo Yikun
• Yao Hongyan
• Cao Linhao
• Wang Sitong

Classifications

• H03M1/86

  with intermediate conversion to frequency of pulses · CPC title

• H03M1/1019

  by storing a corrected or correction value in a digital look-up table · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/0602 Primary

  of deviations from the desired transfer characteristic (H03M1/0617 takes precedence) · CPC title

• H03M1/1009 Primary

  Calibration · CPC title