Multiple port bidirectional power conversion circuit

Patent metadata

Field	Value
Publication number	US-12483136-B2
Application number	US-202318502912-A
Country	US
Kind code	B2
Filing date	Nov 6, 2023
Priority date	Nov 4, 2022
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

In some examples, a circuit includes a first power converter cell and a second power converter cell. The first power converter cell has a first bidirectional interface. The first power converter cell is configured to switch power from the first bidirectional interface to a second bidirectional interface in a first operation mode. The second power converter cell has a third bidirectional interface. The second power converter cell is configured to switch power from the third bidirectional interface to the second bidirectional interface in the first operation mode in parallel with the first power converter cell.

First claim

What is claimed is:

1 . A circuit, comprising:
a first power converter cell, comprising:
a first capacitor having first and second terminals, the first terminal of the first capacitor coupled to a first node and the second terminal of the first capacitor coupled to a second node;
a first inductor having first and second terminals, the first terminal of the first inductor coupled to the first node;
a first switch having a control terminal and first and second terminals, the first terminal of the first switch coupled to the second terminal of the first inductor, and the second terminal of the first switch coupled to the second node; and
a second switch having a control terminal and first and second terminals, the first terminal of the second switch coupled to a third node, and the second terminal of the second switch coupled to the second terminal of the first inductor;
a second power converter cell, comprising:
a second capacitor having first and second terminals, the first terminal of the second capacitor coupled to a fourth node and the second terminal of the second capacitor coupled to the first node;
a second inductor having first and second terminals, the first terminal of the second inductor coupled to the fourth node;
a third switch having a control terminal and first and second terminals, the first terminal of the third switch coupled to the second terminal of the second inductor, and the second terminal of the third switch coupled to the second node; and
a fourth switch having a control terminal and first and second terminals, the first terminal of the fourth switch coupled to the third node, and the second terminal of the fourth switch coupled to the second terminal of the second inductor;
wherein the first and second nodes form a first bidirectional interface, the second and third nodes form a second bidirectional interface, and the first and fourth nodes form a third bidirectional interface; a photovoltaic source coupled to the third bidirectional interface; an energy storage element coupled to the first bidirectional interface; and a load coupled to the second bidirectional interface.

2 . The circuit of claim 1 , wherein the first through fourth switches are each implemented as silicon metal oxide semiconductor field effect transistors.

3 . The circuit of claim 1 , further comprising a controller having a first output coupled to the control terminal of the first switch, a second output coupled to the control terminal of the second switch, a third output coupled to the control terminal of the third switch, and a fourth output coupled to the control terminal of the fourth switch.

4 . The circuit of claim 1 , wherein the circuit is configured to:
receive control signals from a controller at respective control terminals of the first through fourth switches, wherein the control signals cause the first through fourth switches to be configured to:
in a first operation mode, provide power from the first bidirectional interface to the second bidirectional interface while providing power from the third bidirectional interface to the second bidirectional interface;
in a second operation mode, provide power from the third bidirectional interface to the first bidirectional interface and to the second bidirectional interface;
in a third operation mode, provide power from the third bidirectional interface to the first bidirectional interface;
in a fourth operation mode, provide power from the first bidirectional interface to the second bidirectional interface;
in a fifth operation mode, provide power from the second bidirectional interface to the first bidirectional interface; and
in a sixth operation mode, provide power from the third bidirectional interface to the second bidirectional interface without concurrently providing power form the first bidirectional interface to the second bidirectional interface.

5 . The circuit of claim 4 , wherein in the first operation mode, providing power from the first bidirectional interface to the second bidirectional interface while providing power from the third bidirectional interface to the second bidirectional interface reduces a conversion ratio between the first bidirectional interface and the second bidirectional interface.

6 . A circuit, comprising:
a first power converter cell, comprising:
a first capacitor having first and second terminals, the first terminal of the first capacitor coupled to a first node and the second terminal of the first capacitor coupled to a second node;
a first switch having a control terminal and first and second terminals, the first terminal of the first switch coupled to the first node;
a first inductor having first and second terminals, the first terminal of the first inductor coupled to the second terminal of the first switch, and the second terminal of the first inductor coupled to the second node; and
a second switch having a control terminal and first and second terminals, the first terminal of the second switch coupled to the second terminal of the first switch, and the second terminal of the second switch coupled to a third node; and
a second power converter cell, comprising:
a second capacitor having first and second terminals, the first terminal of the second capacitor coupled to a fourth node and the second terminal of the second capacitor coupled to the first node;
a third switch having a control terminal and first and second terminals, the first terminal of the third switch coupled to the fourth node;
a second inductor having first and second terminals, the first terminal of the second inductor coupled to the second terminal of the third switch, and the second terminal of the second inductor coupled to the second node; and
a fourth switch having a control terminal and first and second terminals, the first terminal of the fourth switch coupled to the second terminal of the third switch, and the second terminal of the fourth switch coupled to the third node;
wherein the first and second nodes form a first bidirectional interface, the second and third nodes form a second bidirectional interface, and the first and fourth nodes form a third bidirectional interface; and
wherein the circuit is configured to receive control signals from a controller at respective control terminals of the first through fourth switches, wherein the control signals cause the first through fourth switches to be configured to:
in a first operation mode, provide power from the first bidirectional interface to the second bidirectional interface while providing power from the third bidirectional interface to the second bidirectional interface;
in a second operation mode, provide power from the third bidirectional interface to the first bidirectional interface and to the second bidirectional interface;
in a third operation mode, provide power from the third bidirectional interface to the first bidirectional interface;
in a fourth operation mode, provide power from the first bidirectional interface to the second bidirectional interface;
in a fifth operation mode, provide power from the second bidirectional interface to the first bidirectional interface; and
in a sixth operation mode, provide power from the third bidirectional interface to the second bidirectional interface without concurrently providing power form the first bidirectional interface to the second bidirectional interface.

7 . The circuit of claim 6 , wherein the first through fourth switches are each implemented as silicon metal oxide semiconductor field effect transistors.

8 . The circuit of claim 6 , wherein the controller comprises a first output coupled to the control terminal of the first switch, a second output coupled to the control terminal of the second switch, a third

Assignees

• Univ North Texas

Inventors

• Siu King Man
• Di Wu

Classifications

• H02M3/142

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M1/0067

  Converter structures employing plural converter units, other than for parallel operation of the units on a single load · CPC title

• H02M1/0074

  Plural converter units whose inputs are connected in series · CPC title

• H02M3/33584

  Bidirectional converters · CPC title

• H02M1/008

  Plural converter units for generating at two or more independent and non-parallel outputs, e.g. systems with plural point of load switching regulators · CPC title