System, method and apparatus for reducing power consumption of error correction coding using compacted data blocks

Patent metadata

Field	Value
Publication number	US-12481553-B2
Application number	US-202118572226-A
Country	US
Kind code	B2
Filing date	Dec 17, 2021
Priority date	Dec 17, 2021
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

In one embodiment, an apparatus comprises: a first circuit to compact a plurality of data blocks to a compacted data block and to compact a plurality of error correction codes (ECCs) associated with the plurality of data blocks to a compacted ECC; and a second circuit to generate a generated ECC for the compacted data block. The apparatus may directly send the plurality of data blocks to a destination circuit without error detection on the plurality of data blocks based at least in part on the compacted ECC and the generated ECC. Other embodiments are described and claimed.

First claim

What is claimed is:

1 . An apparatus comprising:
a first circuit to compact a plurality of data blocks to a compacted data block and to compact a plurality of error correction codes (ECCs) associated with the plurality of data blocks to a compacted ECC; and a second circuit to generate a generated ECC for the compacted data block, wherein the apparatus is to directly send the plurality of data blocks to a destination circuit without error detection on the plurality of data blocks based at least in part on the compacted ECC and the generated ECC.

2 . The apparatus of claim 1 , wherein the first circuit comprises N−1 exclusive-OR (XOR) circuits to compact N of the plurality of data blocks.

3 . The apparatus of claim 2 , wherein the first circuit is to generate the compacted data block having X bits, wherein each of the plurality of data blocks has X bits.

4 . The apparatus of claim 1 , further comprising a comparator, wherein the apparatus is to directly send the plurality of data blocks to the destination circuit without the error detection when the comparator determines that the compacted ECC equals the generated ECC.

5 . The apparatus of claim 4 , further comprising an error detection circuit to perform the error detection on at least one of the plurality of data blocks when the compacted ECC does not equal the generated ECC.

6 . The apparatus of claim 5 , further comprising an error correction circuit coupled to the error detection circuit, wherein the error correction circuit is to correct at least one error in at least one of the plurality of data blocks based at least in part on the error detection.

7 . The apparatus of claim 1 , further comprising a control circuit to enable the first circuit and the second circuit in a first mode and to disable at least the first circuit in a second mode.

8 . The apparatus of claim 7 , wherein the control circuit is to disable the first circuit in the second mode in response to a basic input/output system (BIOS) setting.

9 . The apparatus of claim 1 , wherein the apparatus comprises a memory controller having the first circuit and the second circuit, the destination circuit comprising a core.

10 . The apparatus of claim 9 , wherein the memory controller comprises read path circuitry to receive the plurality of data blocks and the plurality of ECCs from a memory in response to a read request from the core.

11 . A method comprising:
compacting, in a memory controller, a plurality of data blocks received from a memory into a compacted data block, and compacting a plurality of error correction codes (ECCs) associated with the plurality of data blocks into a compacted ECC; generating an ECC for the compacted data block; and based at least in part on the ECC and the compacted ECC, directly sending the plurality of data blocks to a destination circuit.

12 . The method of claim 11 , further comprising comparing the ECC to the compacted ECC and directly sending the plurality of data blocks to the destination circuit when the ECC matches the compacted ECC.

13 . The method of claim 12 , further comprising performing error detection on at least one of the plurality of data blocks and not directly sending the plurality of data blocks to the destination circuit when the ECC does not match the compacted ECC.

14 . The method of claim 13 , further comprising in response to detecting an error in at least one of the plurality of data blocks, performing error correction on the at least one data block and thereafter sending the plurality of data blocks to the destination circuit.

15 . The method of claim 11 , further comprising:
compacting the plurality of data blocks and the plurality of ECCs in a first mode; and not compacting a second plurality of data blocks and a second plurality of ECCs in a second mode.

16 . A system comprising:
a processor having at least one core and a memory controller, wherein the memory controller is to:
compact a plurality of data blocks to a compacted data block and compact a plurality of error correction codes (ECCs) associated with the plurality of data blocks to a compacted ECC;
generate a generated ECC for the compacted data block; and
directly send the plurality of data blocks to a requester without error detection on the plurality of data blocks based at least in part on a comparison between the compacted ECC and the generated ECC; and
a memory coupled to the processor, wherein the memory is to send the plurality of data blocks to the memory controller in response to a read request.

17 . The system of claim 16 , wherein the memory is further to send the plurality of ECCs to the memory controller in response to the read request, each of the plurality of data blocks comprising X bits and each of the plurality of ECCs comprising Y bits, Y less than X.

18 . The system of claim 17 , wherein the memory controller is to compact the plurality of data blocks to the compacted data block having X bits and compact the plurality of ECCs to the compacted ECC having Y bits.

19 . The system of claim 16 , wherein the memory controller is to:
directly send the plurality of data blocks to the requester without error detection when the compacted ECC equals the generated ECC; and perform the error detection on the plurality of data blocks when the compacted ECC does not equal the generated ECC.

20 . The system of claim 19 , wherein the memory controller is to correct at least one error in at least one of the plurality of data blocks based at least in part on the error detection.

Assignees

• Intel Corp
• Intel Corportation

Inventors

• Zhuo Qiuxu
• Ananthanarayanan Karthik
• Chen Hsing-Min
• Holm John
• Luck Anthony

Classifications

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title