Display substrate and preparation method thereof, and display apparatus each including partition region provides with at least one partition dam surrounding function hole

US12477932B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12477932-B2
Application numberUS-202117913172-A
CountryUS
Kind codeB2
Filing dateNov 29, 2021
Priority dateNov 29, 2021
Publication dateNov 18, 2025
Grant dateNov 18, 2025

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  1. Title

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  5. First independent claim

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Abstract

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Provided are a display substrate and a preparation method thereof, and a display apparatus. The display substrate includes a display region and at least one hole region located in the display region, the hole region includes a function hole and a partition region surrounding the function hole, the partition region is provided with at least one partition dam surrounding the function hole; the partition dam includes a first partition layer disposed on a base substrate and a second partition layer disposed on a side of the first partition layer away from the base substrate, at least one partition layer includes a second sub-layer and a third sub-layer disposed on a side of the second sub-layer away from the base substrate, the third sub-layer has a protrusion with respect to a sidewall of the second sub-layer, and the protrusion and the sidewall of the second sub-layer form an inwardly recessed structure.

First claim

Opening claim text (preview).

The invention claimed is: 1 . A display substrate, comprising a display region and at least one hole region located in the display region, wherein the hole region comprises a function hole and a partition region surrounding the function hole, and the partition region is provided with at least one partition dam surrounding the function hole; the partition dam comprises a first partition layer disposed on a base substrate and a second partition layer disposed on a side of the first partition layer away from the base substrate, at least one partition layer of the first partition layer and the second partition layer comprises a second sub-layer and a third sub-layer disposed on a side of the second sub-layer away from the base substrate, the third sub-layer has a protrusion with respect to a sidewall of the second sub-layer, the protrusion and the sidewall of the second sub-layer form an inwardly recessed structure, wherein the at least one partition layer further comprises a first sub-layer, and the second sub-layer is disposed on a side of the first sub-layer away from the base substrate, and wherein the first partition layer comprises a first conductive sub-layer, a second conductive sub-layer disposed on a side of the first conductive sub-layer away from the base substrate, and a third conductive sub-layer disposed on a side of the second conductive sub-layer away from the base substrate; along a direction away from the function hole, a width of the second conductive sub-layer is smaller than each of widths of the first conductive sub-layer and the third conductive sub-layer, an orthographic projection of the second conductive sub-layer on the base substrate is within each of a range of an orthographic projection of the first conductive sub-layer and a range of an orthographic projection of the third conductive sub-layer on the base substrate, the first conductive sub-layer and the third conductive sub-layer have protrusions with respect to a sidewall of the second conductive sub-layer, and the protrusions and the sidewall of the second conductive sub-layer form an inwardly recessed structure. 2 . The display substrate according to claim 1 , wherein the second partition layer comprises a first metal sub-layer disposed on a side of the first partition layer away from the base substrate, a second metal sub-layer disposed on a side of the first metal sub-layer away from the base substrate, and a third metal sub-layer disposed on a side of the second metal sub-layer away from the base substrate; along the direction away from the function hole, a width of the second metal sub-layer is smaller than each of widths of the first metal sub-layer and the third metal sub-layer, an orthographic projection of the second metal sub-layer on the base substrate is within each of a range of an orthographic projection of the first metal sub-layer and a range of an orthographic projection of the third metal sub-layer on the base substrate, the first metal sub-layer and the third metal sub-layer have protrusions with respect to a sidewall of the second metal sub-layer, and the protrusions and the sidewall of the second metal sub-layer form an inwardly recessed structure. 3 . The display substrate according to claim 2 , wherein along the direction away from the function hole, a width of the first metal sub-layer is smaller than a width of the first conductive sub-layer, and an orthographic projection of the first metal sub-layer on the base substrate is within a range of an orthographic projection of the first conductive sub-layer on the base substrate. 4 . The display substrate according to claim 2 , wherein along the direction away from the function hole, the width of the second metal sub-layer is smaller than the width of the second conductive sub-layer, and the orthographic projection of the second conductive sub-layer on the base substrate is within a range of an orthographic projection of the second metal sub-layer on the base substrate. 5 . The display substrate according to claim 2 , wherein along the direction away from the function hole, a width of the third metal sub-layer is smaller than a width of the third conductive sub-layer, and an orthographic projection of the third conductive sub-layer on the base substrate is within a range of an orthographic projection of the third metal sub-layer on the base substrate. 6 . The display substrate according to claim 2 , wherein along the direction away from the function hole, a width of the third metal sub-layer is less than or equal to a width of the first metal sub-layer, and an orthographic projection of the third metal sub-layer on the base substrate is within a range of an orthographic projection of the first metal sub-layer on the base substrate; a width of the third conductive sub-layer is less than or equal to a width of the first conductive sub-layer, and an orthographic projection of the third conductive sub-layer on the base substrate is within a range of an orthographic projection of the first conductive sub-layer on the base substrate; the width of the first metal sub-layer is less than or equal to the width of the third conductive sub-layer, and the orthographic projection of the first metal sub-layer on the base substrate is within a range of the orthographic projection of the third conductive sub-layer on the base substrate. 7 . The display substrate according to claim 2 , wherein along the direction away from the function hole, a width of the third metal sub-layer is greater than a width of the first metal sub-layer, and an orthographic projection of the first metal sub-layer on the base substrate is within a range of an orthographic projection of the third metal sub-layer on the base substrate; a width of the third conductive sub-layer is smaller than a width of the first conductive sub-layer, and an orthographic projection of the third conductive sub-layer on the base substrate is within a range of an orthographic projection of the first conductive sub-layer on the base substrate; the width of the first metal sub-layer is equal to the width of the third conductive sub-layer, and the orthographic projection of the first metal sub-layer on the base substrate is substantially overlapped with the orthographic projection of the third conductive sub-layer on the base substrate. 8 . The display substrate according to claim 2 , wherein a distance between an edge of the third metal sub-layer and the base substrate is less than a distance between a surface of the second metal sub-layer on a side away from the base substrate and the base substrate. 9 . The display substrate according to claim 1 , wherein the second partition layer comprises a first metal sub-layer disposed on a side of the first partition layer away from the base substrate, a second metal sub-layer disposed on a side of the first metal sub-layer away from the base substrate, and a third metal sub-layer disposed on a side of the second metal sub-layer away from the base substrate; a cross-sectional shape of the second metal sub-layer is a second trapezoid, the second trapezoid comprises a second lower bottom on a side close to the base substrate and a second upper bottom on a side away from the base substrate; along the direction away from the function hole, a width of the second upper bottom is smaller than a width of the second lower bottom, an orthographic projection of the second upper bottom on the base substrate is within a range of an orthographic projection of the second lower bottom on the base substrate; a width of the third metal sub-layer is less than or equal to the width of the second upper bottom, and an orthographic projection of the third metal sub-layer on the base substrate is within a range of the orthographic projection of

Assignees

Inventors

Classifications

  • Manufacture or treatment · CPC title

  • OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes · CPC title

  • Constructional details · CPC title

  • Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00 · CPC title

  • OLEDs integrated with inorganic image sensors · CPC title

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What does patent US12477932B2 cover?
Provided are a display substrate and a preparation method thereof, and a display apparatus. The display substrate includes a display region and at least one hole region located in the display region, the hole region includes a function hole and a partition region surrounding the function hole, the partition region is provided with at least one partition dam surrounding the function hole; the pa…
Who is the assignee on this patent?
Chengdu Boe Optoelect Tech Co, Boe Technology Group Co Ltd, Beijing Boe Technology Dev Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10K59/873. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 18 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).